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-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb6
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb6
2 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 501aa2a160..82303c6ddf 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
+ # Enable RP LTR
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+
# Hybrid storage mode
register "HybridStorageMode" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 81d52a8d3d..043185bfdd 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
+ # Enable PR LTR
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+
# Hybrid storage mode
register "HybridStorageMode" = "1"