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-rw-r--r--src/mainboard/intel/d810e2cb/romstage.c3
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c2
2 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index fcdbb3156e..81e2d5d348 100644
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -35,9 +35,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-
void main(unsigned long bist)
{
/* Set southbridge and Super I/O GPIOs. */
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 8b79f2dc57..8b02163ab8 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -39,8 +39,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-void enable_smbus(void);
-
void setup_ich7_gpios(void)
{
/* TODO: This is highly board specific and should be moved */