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-rw-r--r--src/mainboard/iwill/dk8_htx/Config.lb14
-rw-r--r--src/mainboard/iwill/dk8_htx/Options.lb14
-rw-r--r--src/mainboard/iwill/dk8s2/Config.lb14
-rw-r--r--src/mainboard/iwill/dk8s2/Options.lb14
-rw-r--r--src/mainboard/iwill/dk8x/Config.lb14
-rw-r--r--src/mainboard/iwill/dk8x/Options.lb14
6 files changed, 42 insertions, 42 deletions
diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
index 31f3236d51..99ad24b981 100644
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ b/src/mainboard/iwill/dk8_htx/Config.lb
@@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@@ -162,7 +162,7 @@ else
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
@@ -189,7 +189,7 @@ if USE_DCACHE_RAM
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@@ -223,7 +223,7 @@ if USE_DCACHE_RAM
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb
index 713c8ad54d..6d8eab4d0c 100644
--- a/src/mainboard/iwill/dk8_htx/Options.lb
+++ b/src/mainboard/iwill/dk8_htx/Options.lb
@@ -40,7 +40,7 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@@ -122,7 +122,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@@ -149,7 +149,7 @@ default ACPI_SSDTX_NUM=3
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@@ -236,10 +236,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@@ -258,7 +258,7 @@ default HEAP_SIZE=0x8000
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
@@ -308,7 +308,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb
index 59312df508..4cb18e5757 100644
--- a/src/mainboard/iwill/dk8s2/Config.lb
+++ b/src/mainboard/iwill/dk8s2/Config.lb
@@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@@ -95,7 +95,7 @@ end
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@@ -115,7 +115,7 @@ if USE_DCACHE_RAM
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -145,7 +145,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb
index 10e89d88b4..81aa84ef7e 100644
--- a/src/mainboard/iwill/dk8s2/Options.lb
+++ b/src/mainboard/iwill/dk8s2/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@@ -72,7 +72,7 @@ default FALLBACK_SIZE=0x40000
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@@ -94,7 +94,7 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@@ -131,10 +131,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@@ -153,7 +153,7 @@ default HEAP_SIZE=0x4000
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@@ -202,7 +202,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb
index 30f7c3ce50..6eece3e320 100644
--- a/src/mainboard/iwill/dk8x/Config.lb
+++ b/src/mainboard/iwill/dk8x/Config.lb
@@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@@ -92,7 +92,7 @@ end
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -142,7 +142,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb
index 4c982f2242..1811aa44c5 100644
--- a/src/mainboard/iwill/dk8x/Options.lb
+++ b/src/mainboard/iwill/dk8x/Options.lb
@@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@@ -72,7 +72,7 @@ default FALLBACK_SIZE=131072
default HAVE_FALLBACK_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@@ -94,7 +94,7 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@@ -130,10 +130,10 @@ default CONFIG_USE_INIT=0
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@@ -152,7 +152,7 @@ default HEAP_SIZE=0x4000
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
@@ -201,7 +201,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 13:35:24 +0000