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Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c37
1 files changed, 1 insertions, 36 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index cb01046010..d67a60b1e8 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -165,40 +165,7 @@ static void rcba_config(void)
RCBA16(D28IR) = 0x3210;
RCBA16(D27IR) = 0x3210;
- /* Enable IOAPIC */
- RCBA8(OIC) = 0x03;
-
/* Enable PCIe Root Port Clock Gate */
-
-}
-
-static void early_ich7_init(void)
-{
- uint8_t reg8;
- uint32_t reg32;
-
- /* program secondary mlt XXX byte? */
- pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
- /* reset rtc power status */
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- reg8 &= ~RTC_BATTERY_DEAD;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
- /* usb transient disconnect */
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
- ich7_setup_cir();
}
void mainboard_romstage_entry(void)
@@ -221,6 +188,7 @@ void mainboard_romstage_entry(void)
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
+ i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
@@ -233,9 +201,6 @@ void mainboard_romstage_entry(void)
sdram_initialize(s3resume ? 2 : 0, NULL);
- /* Perform some initialization that must run before stage2 */
- early_ich7_init();
-
/* This should probably go away. Until now it is required
* and mainboard specific
*/