diff options
Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Config.lb | 7 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Options.lb | 2 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/acpi/superio.asl | 46 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/acpi_tables.c | 124 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/auto.c | 99 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/cmos.layout | 56 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/dsdt.asl | 14 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/fadt.c | 34 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/mainboard.c | 161 |
11 files changed, 402 insertions, 146 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index 0dc004055c..eab88a9589 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -55,7 +55,8 @@ if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o makerule dsdt.c depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" + action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" + action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" action "mv $(CURDIR)/dsdt.hex dsdt.c" end object ./dsdt.o @@ -150,7 +151,8 @@ chip northbridge/intel/i945 device pci_domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port + # autodetect 0:1.0 because it might or might not be there. + # device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller # register "rom_address" = "0xfffc0000" # 256 KB image @@ -174,6 +176,7 @@ chip northbridge/intel/i945 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" + register "gpe0_en" = "0x00000400" register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 6ac6be2e2f..2af7401c55 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -43,7 +43,7 @@ config LB_CKS_LOC config MAINBOARD_PART_NUMBER string - default "986LCD-M/mITX" + default "986LCD-M" depends on BOARD_KONTRON_986LCD_M config MMCONF_BASE_ADDRESS diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc index 61acbe68ca..5cd84bcde7 100644 --- a/src/mainboard/kontron/986lcd-m/Makefile.inc +++ b/src/mainboard/kontron/986lcd-m/Makefile.inc @@ -56,7 +56,8 @@ ldscript-y += ../../../../src/arch/i386/lib/failover.lds ifdef POST_EVALUATION $(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl - iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src)/mainboard/$(MAINBOARDDIR) $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl -o $(obj)/dsdt.asl + iasl -p dsdt -tc $(obj)/dsdt.asl mv dsdt.hex $@ $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb index feb26a666a..811d8efdb3 100644 --- a/src/mainboard/kontron/986lcd-m/Options.lb +++ b/src/mainboard/kontron/986lcd-m/Options.lb @@ -312,7 +312,7 @@ default CONFIG_TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages +## DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output diff --git a/src/mainboard/kontron/986lcd-m/acpi/superio.asl b/src/mainboard/kontron/986lcd-m/acpi/superio.asl index d2498d4e5b..bb927afb01 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/superio.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/superio.asl @@ -29,7 +29,30 @@ Device (SIO1) { Name(_HID, EISAID("PNP0501")) Name(_UID, 1) + Name(_DDN, "COM1") + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } // Some methods need an implementation here: // missing: _STA, _DIS, _CRS, _PRS, // missing: _SRS, _PS0, _PS3 @@ -39,7 +62,30 @@ Device (SIO1) { Name(_HID, EISAID("PNP0501")) Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } // Some methods need an implementation here: // missing: _STA, _DIS, _CRS, _PRS, // missing: _SRS, _PS0, _PS3 diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 27942e3499..68f3d9cbf9 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -31,100 +31,33 @@ #include <cpu/x86/msr.h> #include "dmi.h" -#define OLD_ACPI 0 - extern unsigned char AmlCode[]; #if HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif void generate_cpu_entries(void); // from cpu/intel/speedstep -unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945 - -#if OLD_ACPI -typedef struct acpi_oemb { - acpi_header_t header; - u8 ss; - u16 iost; - u32 topm; - u32 roms; - u32 mg1b; - u32 mg1l; - u32 mg2b; - u32 mg2l; - u8 rsvd; - u8 dmax; - u32 hpta; - u32 cpb0; - u32 cpb1; - u32 cpb2; - u32 cpb3; - u8 assb; - u8 aotb; - u32 aaxb; - u8 smif; - u8 dtse; - u8 dts1; - u8 dts2; - u8 mpen; -} __attribute__((packed)) acpi_oemb_t; -#endif - -typedef struct acpi_gnvs { - // 0x00 - u16 osys; - u8 smif; - u8 reserved[13]; - // 0x10 - u8 mpen; -} __attribute__((packed)) acpi_gnvs_t; - -#if OLD_ACPI -void acpi_create_oemb(acpi_oemb_t *oemb) -{ - acpi_header_t *header = &(oemb->header); - unsigned long tolud; - - memset (oemb, 0, sizeof(*oemb)); - - /* fill out header fields */ - memcpy(header->signature, "OEMB", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, ASLC, 4); - - header->length = sizeof(acpi_oemb_t); - header->revision = 1; - - oemb->ss = 0x09; // ss1 + ss 4 - oemb->iost = 0x0403; // ?? - - tolud = pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c); - oemb->topm = tolud; - - oemb->roms = 0xfff00000; // 1M hardcoded - - oemb->mg1b = 0x000d0000; - oemb->mg1l = 0x00010000; - oemb->mg2b = tolud; - oemb->mg2l = 0-tolud; - - oemb->dmax = 0x87; - oemb->hpta = 0x000e36c0; - - header->checksum = - acpi_checksum((void *) oemb, sizeof(acpi_oemb_t)); - -}; -#endif - -void acpi_create_gnvs(acpi_gnvs_t *gnvs) +#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->mpen = 1; + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) { #define HPET_ADDR 0xfed00000ULL acpi_header_t *header = &(hpet->header); @@ -212,10 +145,6 @@ unsigned long write_acpi_tables(unsigned long start) #if HAVE_ACPI_SLIC acpi_header_t *slic; #endif -#if OLD_ACPI - acpi_oemb_t *oemb; -#endif - acpi_gnvs_t *gnvs; acpi_header_t *ssdt; acpi_header_t *dsdt; @@ -271,15 +200,6 @@ unsigned long write_acpi_tables(unsigned long start) ALIGN_CURRENT; acpi_add_table(rsdp, mcfg); -#if OLD_ACPI - printk_debug("ACPI: * OEMB\n"); - oemb=(acpi_oemb_t *)current; - current += sizeof(acpi_oemb_t); - ALIGN_CURRENT; - acpi_create_oemb(oemb); - acpi_add_table(rsdp, oemb); -#endif - printk_debug("ACPI: * FACS\n"); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); @@ -291,16 +211,6 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *) dsdt, (void *) AmlCode, ((acpi_header_t *) AmlCode)->length); -#if OLD_ACPI - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBEEF) { - printk_debug("ACPI: Patching up DSDT at offset 0x%04x -> 0x%08x\n", i, 0x24 + (u32)oemb); - *(u32*)(((u32)dsdt) + i) = 0x24 + (u32)oemb; - break; - } - } -#endif - ALIGN_CURRENT; /* Pack GNVS into the ACPI table area */ diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c index d83f0fec2a..003fdb393f 100644 --- a/src/mainboard/kontron/986lcd-m/auto.c +++ b/src/mainboard/kontron/986lcd-m/auto.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -57,7 +57,6 @@ #include "southbridge/intel/i82801gx/i82801gx.h" static void setup_ich7_gpios(void) { - /* TODO: This is highly board specific and should be moved */ printk_debug(" GPIOS..."); /* General Registers */ outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ @@ -127,6 +126,12 @@ static void early_superio_config_w83627thg(void) dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, 0x24, 0xc6); // PNPCSV + + pnp_write_config(dev, 0x29, 0x43); // GPIO settings + pnp_write_config(dev, 0x2a, 0x40); // GPIO settings + + dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); @@ -218,6 +223,8 @@ static void early_superio_config_w83627thg(void) static void rcba_config(void) { + u32 reg32; + /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; @@ -240,9 +247,52 @@ static void rcba_config(void) /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); + /* Now, this is a bit ugly. As per PCI specification, function 0 of a + * device always has to be implemented. So disabling ethernet port 1 + * would essentially disable all three ethernet ports of the mainboard. + * It's possible to rename the ports to achieve compatibility to the + * PCI spec but this will confuse all (static!) tables containing + * interrupt routing information. + * To avoid this, we enable (unused) port 6 and swap it with port 1 + * in the case that ethernet port 1 is disabled. Since no devices + * are connected to that port, we don't have to worry about interrupt + * routing. + */ + int port_shuffle = 0; + /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA; - RCBA32(0x3418) |= (1 << 0); // Required. + reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; + reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; + + if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { + printk_debug("Disabling ethernet adapter 1.\n"); + reg32 |= FD_PCIE1; + } + if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { + printk_debug("Disabling ethernet adapter 2.\n"); + reg32 |= FD_PCIE2; + } else { + if (reg32 & FD_PCIE1) + port_shuffle = 1; + } + if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { + printk_debug("Disabling ethernet adapter 3.\n"); + reg32 |= FD_PCIE3; + } else { + if (reg32 & FD_PCIE1) + port_shuffle = 1; + } + + if (port_shuffle) { + /* Enable PCIE6 again */ + reg32 &= ~FD_PCIE6; + /* Swap PCIE6 and PCIE1 */ + RCBA32(RPFN) = 0x00043215; + } + + reg32 |= 1; + + RCBA32(0x3418) = reg32; /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; @@ -306,6 +356,16 @@ static void early_ich7_init(void) #include "southbridge/intel/i82801gx/cmos_failover.c" #endif +#include <cbmem.h> + +// Now, this needs to be included because it relies on the symbol +// __ROMCC_ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + void real_main(unsigned long bist) { u32 reg32; @@ -345,13 +405,14 @@ void real_main(unsigned long bist) reg32 = inl(DEFAULT_PMBASE + 0x04); printk_debug("PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME printk_debug("Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + #else printk_debug("Resume from S3 detected, but disabled.\n"); #endif @@ -380,6 +441,7 @@ void real_main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); +#if !CONFIG_HAVE_ACPI_RESUME #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 #if defined(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); @@ -391,10 +453,35 @@ void real_main(unsigned long bist) printk_debug("TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); + //ram_check(0x00100000, tom); } #endif +#endif + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } +#endif } #include "cpu/intel/model_6ex/cache_as_ram_disable.c" diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index a53381c7a3..1a19018b5e 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -91,7 +91,21 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 80 r 0 unused +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -135,7 +149,45 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep - +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (°C/°F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index f12e16b9a4..04a658fe90 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -29,24 +29,24 @@ DefinitionBlock( ) { // Some generic macros - Include ("acpi/platform.asl") + #include "acpi/platform.asl" // global NVS and variables - Include ("../../../southbridge/intel/i82801gx/acpi/globalnvs.asl") + #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" // General Purpose Events - //include ("acpi/gpe.asl") + //#include "acpi/gpe.asl" - //include ("acpi/thermal.asl") + //#include "acpi/thermal.asl" Scope (\_SB) { Device (PCI0) { - Include ("../../../northbridge/intel/i945/acpi/i945.asl") - include ("../../../southbridge/intel/i82801gx/acpi/ich7.asl") + #include "../../../northbridge/intel/i945/acpi/i945.asl" + #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" } } /* Chipset specific sleep states */ - include ("../../../southbridge/intel/i82801gx/acpi/sleepstates.asl") + #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" } diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c index e8677e1015..72d94332ef 100644 --- a/src/mainboard/kontron/986lcd-m/fadt.c +++ b/src/mainboard/kontron/986lcd-m/fadt.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,13 +23,13 @@ #include <device/pci.h> #include <arch/acpi.h> -/* FIXME: This needs to go into a separate .h file +/* FIXME: This needs to go into a separate .h file * to be included by the ich7 smi handler, ich7 smi init * code and the mainboard fadt. */ #define APM_CNT 0xb2 -#define CST_CONTROL 0x00 // 0xe3 crashes the box -#define PST_CONTROL 0x00 // 0xe2 crashes the box +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 #define ACPI_DISABLE 0x1e #define ACPI_ENABLE 0xe1 #define GNVS_UPDATE 0xea @@ -59,7 +59,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->acpi_disable = ACPI_DISABLE; fadt->s4bios_req = 0x0; fadt->pstate_cnt = PST_CONTROL; - + fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; fadt->pm1a_cnt_blk = pmbase + 0x4; @@ -89,72 +89,72 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->century = 0x00; fadt->iapc_boot_arch = 0x03; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - + fadt->reset_reg.space_id = 0; fadt->reset_reg.bit_width = 0; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.resv = 0; fadt->reset_reg.addrl = 0x0; fadt->reset_reg.addrh = 0x0; - + fadt->reset_value = 0; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - + fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; - + fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.resv = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - + fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; - + fadt->x_pm1b_cnt_blk.space_id = 1; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.resv = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - + fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; fadt->x_pm2_cnt_blk.addrh = 0x0; - + fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; - + fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0; - + fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 4cc883efeb..9a2a5fdc5c 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,10 +19,12 @@ * MA 02110-1301 USA */ - +#include <types.h> #include <device/device.h> #include <console/console.h> #include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include <arch/io.h> #include "chip.h" int add_northbridge_resources(struct lb_memory *mem); @@ -32,7 +34,162 @@ int add_mainboard_resources(struct lb_memory *mem) return add_northbridge_resources(mem); } +/* Hardware Monitor */ + +static u16 hwm_base = 0xa00; + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, hwm_base + 0x05); + outb(value, hwm_base + 0x06); +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +static void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") < 0) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") < 0) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") < 0) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") < 0) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk_debug("Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk_debug("Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk_debug("Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk_debug("Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} + +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). +static void mainboard_enable(device_t dev) +{ + verb_setup(); + hwm_setup(); +} + struct chip_operations mainboard_ops = { CHIP_NAME("Kontron 986LCD-M Mainboard") + .enable_dev = mainboard_enable, }; |