diff options
Diffstat (limited to 'src/mainboard/lenovo/t430s')
| -rw-r--r-- | src/mainboard/lenovo/t430s/cmos.default | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t430s/cmos.layout | 3 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t430s/romstage.c | 18 |
3 files changed, 21 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 979f132863..3e1f130ce4 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -13,4 +13,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable backlight=Both +enable_dual_graphics=Disable usb_always_on=Disable diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 538e624350..97d97ed349 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -76,7 +76,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 1 e 1 enable_dual_graphics +#436 4 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 3f6d9f2836..633ba3f142 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -15,12 +15,14 @@ * GNU General Public License for more details. */ +#include <option.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/pmh7/pmh7.h> void pch_enable_lpc(void) { @@ -64,6 +66,22 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { } void mainboard_early_init(int s3resume) { + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_PEG10; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } } void mainboard_config_superio(void) |