summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/x220/devicetree.cb
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/lenovo/x220/devicetree.cb')
-rw-r--r--src/mainboard/lenovo/x220/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 8f4deaa2a4..3edbb87a08 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -77,6 +77,9 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+
device pci 16.0 on
subsystemid 0x17aa 0x21db
end # Management Engine Interface 1