diff options
Diffstat (limited to 'src/mainboard/lenovo/x60/i915io.c')
| -rw-r--r-- | src/mainboard/lenovo/x60/i915io.c | 2273 |
1 files changed, 2273 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c new file mode 100644 index 0000000000..9b21094a3b --- /dev/null +++ b/src/mainboard/lenovo/x60/i915io.c @@ -0,0 +1,2273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "i915io.h" + +struct iodef iodefs[] = { +{V,0,}, +{M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0}, +{M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0}, +{M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0}, +{M, 1, "agpgart-intel 0000:00:00.0:detected 8192K stolen memory", 0x0, 0x0, 0}, +{M, 1, "agpgart-intel 0000:00:00.0:AGP aperture is 256M @ 0xd0000000", 0x0, 0x0, 0}, +{M, 1, "[drm] Initialized drm 1.1.0 20060810", 0x0, 0x0, 0}, +{M, 1, "[drm] radeon defaulting to kernel modesetting.", 0x0, 0x0, 0}, +{M, 1, "[drm] radeon kernel modesetting enabled.", 0x0, 0x0, 0}, +{M, 1, "i915 0000:00:02.0:setting latency timer to 64", 0x0, 0x0, 0}, +{W, 1, "", 0x5100, 0x00000000, 0}, +{R, 1, "", PP_ON_DELAYS, 0x00000000, 0}, +{R, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, +{W, 1, "", PP_ON_DELAYS, 0x00000000, 0}, +{W, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, +{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE |0x08000800, 0}, +{W, 1, "", RENDER_RING_BASE, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0xc, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x10, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x14, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x18, 0x00000000, 0}, +{W, 1, "", RENDER_RING_BASE+0x1c, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x4, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x8, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0xc, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x10, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0}, +{W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0}, +{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 |0x000f0202, 0}, +{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0}, +{M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0}, +{M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0}, +{M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0}, +{M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0}, +{W, 1, "", VGACNTRL, VGA_DISP_DISABLE |0x80000000, 0}, +{R, 1, "", PFIT_CONTROL, 0x00000000, 0}, +{W, 1, "", 0x5100, 0x00000003, 0}, +{W, 1, "", 0x5104, 0x460100a1, 0}, +{R, 1, "", 0x5108, 0x00004a00, 0}, +{R, 1, "", 0x510c, 0x00000000, 0}, +{R, 1, "", 0x5108, 0x0000c200, 0}, +{W, 1, "", 0x5104, 0x48000000, 0}, +{R, 1, "", 0x5108, 0x00008800, 0}, +{W, 1, "", 0x5100, 0x00000000, 0}, +{W, 1, "", 0x5100, 0x00000003, 0}, +{W, 1, "", 0x5104, 0x468000a1, 0}, +{R, 1, "", 0x5108, 0x00008a08, 0}, +{R, 1, "", 0x510c, 0xffffff00, 0}, +{R, 1, "", 0x5108, 0x00008a0c, 0}, +{R, 1, "", 0x510c, 0x00ffffff, 0}, +{R, 1, "", 0x5108, 0x00008a10, 0}, +{R, 1, "", 0x510c, 0x4000ae30, 0}, +{R, 1, "", 0x5108, 0x00008a14, 0}, +{R, 1, "", 0x510c, 0x00000000, 0}, +{R, 1, "", 0x5108, 0x00008a18, 0}, +{R, 1, "", 0x510c, 0x03010f00, 0}, +{R, 1, "", 0x5108, 0x00008a1c, 0}, +{R, 1, "", 0x510c, 0x78121980, 0}, +{R, 1, "", 0x5108, 0x00008a20, 0}, +{R, 1, "", 0x510c, 0x9175edea, 0}, +{R, 1, "", 0x5108, 0x00008a24, 0}, +{R, 1, "", 0x510c, 0x268b4f57, 0}, +{R, 1, "", 0x5108, 0x00008a28, 0}, +{R, 1, "", 0x510c, 0x21545021, 0}, +{R, 1, "", 0x5108, 0x00008a2c, 0}, +{R, 1, "", 0x510c, 0x01010008, 0}, +{R, 1, "", 0x5108, 0x00008a30, 0}, +{R, 1, "", 0x510c, 0x01010101, 0}, +{R, 1, "", 0x5108, 0x00008a34, 0}, +{R, 1, "", 0x510c, 0x01010101, 0}, +{R, 1, "", 0x5108, 0x00008a38, 0}, +{R, 1, "", 0x510c, 0x01010101, 0}, +{R, 1, "", 0x5108, 0x00008a3c, 0}, +{R, 1, "", 0x510c, 0x15280101, 0}, +{R, 1, "", 0x5108, 0x00008a40, 0}, +{R, 1, "", 0x510c, 0x00414000, 0}, +{R, 1, "", 0x5108, 0x00008a44, 0}, +{R, 1, "", 0x510c, 0x88183026, 0}, +{R, 1, "", 0x5108, 0x00008a48, 0}, +{R, 1, "", 0x510c, 0xb9f60036, 0}, +{R, 1, "", 0x5108, 0x00008a4c, 0}, +{R, 1, "", 0x510c, 0x18000000, 0}, +{R, 1, "", 0x5108, 0x00008a50, 0}, +{R, 1, "", 0x510c, 0x400010ed, 0}, +{R, 1, "", 0x5108, 0x00008a54, 0}, +{R, 1, "", 0x510c, 0x30260041, 0}, +{R, 1, "", 0x5108, 0x00008a58, 0}, +{R, 1, "", 0x510c, 0x00368818, 0}, +{R, 1, "", 0x5108, 0x00008a5c, 0}, +{R, 1, "", 0x510c, 0x0000b9f6, 0}, +{R, 1, "", 0x5108, 0x00008a60, 0}, +{R, 1, "", 0x510c, 0x00001800, 0}, +{R, 1, "", 0x5108, 0x00008a64, 0}, +{R, 1, "", 0x510c, 0x61000f00, 0}, +{R, 1, "", 0x5108, 0x00008a68, 0}, +{R, 1, "", 0x510c, 0x43613243, 0}, +{R, 1, "", 0x5108, 0x00008a6c, 0}, +{R, 1, "", 0x510c, 0x00010f28, 0}, +{R, 1, "", 0x5108, 0x00008a70, 0}, +{R, 1, "", 0x510c, 0x4a58a34c, 0}, +{R, 1, "", 0x5108, 0x00008a74, 0}, +{R, 1, "", 0x510c, 0xfe000000, 0}, +{R, 1, "", 0x5108, 0x00008a78, 0}, +{R, 1, "", 0x510c, 0x4e544c00, 0}, +{R, 1, "", 0x5108, 0x00008a7c, 0}, +{R, 1, "", 0x510c, 0x58313231, 0}, +{R, 1, "", 0x5108, 0x0000ca00, 0}, +{R, 1, "", 0x510c, 0x304c2d4a, 0}, +{R, 1, "", 0x5108, 0x0000ca00, 0}, +{R, 1, "", 0x510c, 0x00000a37, 0}, +{R, 1, "", 0x5108, 0x0000c200, 0}, +{W, 1, "", 0x5104, 0x48000000, 0}, +{R, 1, "", 0x5108, 0x00008800, 0}, +{W, 1, "", 0x5100, 0x00000000, 0}, +{R, 1, "", PP_CONTROL, 0x00000000, 0}, +{W, 1, "", PP_CONTROL, 0xabcd0000, 0}, +{R, 2, "", BLC_PWM_CTL, 0x00000000, 0}, +{R, 2, "", DVOB, 0x00300000, 0}, +{R, 1, "", DVOC, 0x00300000, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{R, 1, "", TV_DAC, 0x00000000, 0}, +{W, 1, "", TV_DAC, 0x08000000, 0}, +{R, 1, "", TV_DAC, 0x08000000, 0}, +{W, 1, "", TV_DAC, 0x00000000, 0}, +{R, 1, "", TV_DAC, 0x00000000, 0}, +{W, 1, "", TV_DAC, 0x00000000, 0}, +{M, 1, "tsc:Refined TSC clocksource calibration:1662.499 MHz", 0x0, 0x0, 0}, +{W, 1, "", HWS_PGA, 0x352d2000, 0}, +{W, 1, "", PRB0_CTL, 0x00000000, 0}, +{M, 1, "Switching to clocksource tsc", 0x0, 0x0, 0}, +{W, 1, "", PRB0_HEAD, 0x00000000, 0}, +{W, 1, "", PRB0_TAIL, 0x00000000, 0}, +{R, 1, "", PRB0_HEAD, 0x00000000, 0}, +{W, 1, "", PRB0_START, 0x00000000, 0}, +{W, 1, "", PRB0_CTL, 0x0001f001, 0}, +{R, 1, "", PRB0_CTL, 0x0001f001, 0}, +{R, 1, "", PRB0_START, 0x00000000, 0}, +{R, 2, "", PRB0_HEAD, 0x00000000, 0}, +{R, 1, "", PRB0_TAIL, 0x00000000, 0}, +{R, 1, "", 0x6104, 0x00000000, 0}, +{W, 1, "", 0x6104, 0x0000000b, 0}, +{W, 1, "", ECOSKPD, 0x00010000, 0}, +{M, 1, "[drm] initialized overlay support", 0x0, 0x0, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{R, 1, "", _PIPEBCONF, 0x00000000, 0}, +{R, 1, "", LVDS, 0x40000000, 0}, +{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{R, 1, "", LVDS, 0x40000000, 0}, +{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{W, 1, "", _PIPEACONF, 0x00000000, 0}, +{R, 1, "", _DSPACNTR, 0x00000000, 0}, +{R, 1, "", _PIPEBCONF, 0x00000000, 0}, +{W, 1, "", _PIPEBCONF, 0x00000000, 0}, +{R, 1, "", _DSPBCNTR, 0x00000000, 0}, +{R, 1, "", LVDS, 0x40000000, 0}, +{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{R, 1, "", LVDS, 0x40000000, 0}, +{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{R, 1, "", _PIPEBCONF, 0x00000000, 0}, +{W, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, +{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, +{W, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, +{W, 1, "", HWSTAM, 0x0000effe, 0}, +{W, 1, "", _PIPEASTAT, 0x00000000, 0}, +{W, 1, "", _PIPEBSTAT, 0x00000000, 0}, +{W, 1, "", IMR, 0xffffffff, 0}, +{W, 1, "", IER, 0x00000000, 0}, +{W, 1, "", EMR, 0xffffffed, 0}, +{W, 1, "", IMR, 0xfffd73ae, 0}, +{W, 1, "", IER, 0x00028053, 0}, +{R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, +{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0}, +{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0}, +{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0}, +{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0}, +{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0}, +{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, +{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS |0x00000800, 0}, +{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0}, +{W, 1, "", 0x5100, 0x00000002, 0}, +{W, 1, "", 0x5104, 0x460100a1, 0}, +{R, 2, "", 0x5108, 0x00009c00, 0}, +{W, 1, "", 0x5104, 0x80000000, 0}, +{W, 1, "", 0x5104, 0x00000000, 0}, +{W, 2, "", 0x5100, 0x00000000, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{W, 1, "", _FPA0, 0x00020e08, 0}, +{W, 1, "", _FPA1, 0x00020e08, 0}, +{W, 1, "", _DPLL_A, 0x14020003, 0}, +{W, 2, "", _DPLL_A, 0x94020003, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{W, 1, "", _HTOTAL_A, 0x06af04ff, 0}, +{W, 1, "", _HBLANK_A, 0x06af04ff, 0}, +{W, 1, "", _HSYNC_A, 0x05d70557, 0}, +{W, 1, "", _VTOTAL_A, 0x044f03ff, 0}, +{W, 1, "", _VBLANK_A, 0x044f03ff, 0}, +{W, 1, "", _VSYNC_A, 0x04090402, 0}, +{W, 1, "", _PIPEASRC, 0x04ff03ff, 0}, +{W, 1, "", _DSPBSIZE, 0x03ff04ff, 0}, +{W, 1, "", _DSPBPOS, 0x00000000, 0}, +{W, 1, "", _PIPEACONF, 0x00000000, 0}, +{R, 1, "", _DPLL_A, 0x94020003, 0}, +{R, 1, "", _PIPEACONF, 0x00000000, 0}, +{W, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0}, +{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0}, +{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0}, +{R, 2, "", _PIPEASTAT, 0x00000000, 0}, +{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0}, +{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0}, +{R, 1, "", _PIPEASTAT, 0x00000000, 0}, +{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0}, +{W, 1, "", _DSPBCNTR, 0x40000000, 0}, +{R, 1, "", _DSPBCNTR, 0x40000000, 0}, +{W, 1, "", _DSPBCNTR, 0x58000000, 0}, +{W, 1, "", _DSPBSTRIDE, 0x00001400, 0}, +{W, 1, "", _DSPBADDR, 0x00020000, 0}, +{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0}, +{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK |0x80000000, 0}, +{W, 1, "", FW_BLC, 0x011d011a, 0}, +{W, 1, "", FW_BLC2, 0x00000102, 0}, +{R, 1, "", TV_CTL, 0x00000000, 0}, +{W, 1, "", TV_H_CTL_1, 0x00400359, 0}, +{W, 1, "", TV_H_CTL_2, 0x80480022, 0}, +{W, 1, "", TV_H_CTL_3, 0x007c0344, 0}, +{W, 1, "", TV_V_CTL_1, 0x00f01415, 0}, +{W, 1, "", TV_V_CTL_2, 0x00060607, 0}, +{W, 1, "", TV_V_CTL_3, 0x80120001, 0}, +{W, 1, "", TV_V_CTL_4, 0x000900f0, 0}, +{W, 1, "", TV_V_CTL_5, 0x000a00f0, 0}, +{W, 1, "", TV_V_CTL_6, 0x000900f0, 0}, +{W, 1, "", TV_V_CTL_7, 0x000a00f0, 0}, +{W, 1, "", TV_SC_CTL_1, 0xc1710087, 0}, +{W, 1, "", TV_SC_CTL_2, 0x6b405140, 0}, +{W, 1, "", TV_SC_CTL_3, 0x00000000, 0}, +{W, 1, "", TV_CSC_Y, 0x0332012d, 0}, +{W, 1, "", TV_CSC_Y2, 0x07d30104, 0}, +{W, 1, "", TV_CSC_U, 0x0733052d, 0}, +{W, 1, "", TV_CSC_U2, 0x05c70200, 0}, +{W, 1, "", TV_CSC_V, 0x0340030c, 0}, +{W, 1, "", TV_CSC_V2, 0x06d00200, 0}, +{W, 1, "", TV_CLR_KNOBS, 0x00606000, 0}, +{W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0}, +{R, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0}, +{R, 1, "", _DSPBCNTR, 0x58000000, 0}, +{W, 1, "", _DSPBCNTR, 0x58000000, 0}, +{R, 1, "", _DSPBADDR, 0x00020000, 0}, +{W, 1, "", _DSPBADDR, 0x00020000, 0}, +{W, 1, "", _PIPEACONF, 0x00000000, 0}, +{R, 1, "", _PIPEADSL, 0x0000029e, 0}, +{R, 3, "", _PIPEADSL, 0x000003ff, 0}, +{W, 1, "", _PFA_CTL_1, 0x80000000, 0}, +{W, 1, "", _PFA_WIN_POS, 0x00360024, 0}, +{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0}, +{W, 1, "", _PIPEACONF, PIPECONF_ENABLE |0x80000000, 0}, +{W, 1, "", _DSPBCNTR, 0x58000000, 0}, +{R, 1, "", _DSPBADDR, 0x00020000, 0}, +{W, 1, "", _DSPBADDR, 0x00020000, 0}, +{W, 1, "", TV_H_LUMA_0, 0xb1403000, 0}, +{W, 1, "", TV_H_LUMA_0+0x4, 0x2e203500, 0}, +{W, 1, "", TV_H_LUMA_0+0x8, 0x35002e20, 0}, +{W, 1, "", TV_H_LUMA_0+0xc, 0x3000b140, 0}, +{W, 1, "", TV_H_LUMA_0+0x10, 0x35a0b160, 0}, +{W, 1, "", TV_H_LUMA_0+0x14, 0x2dc02e80, 0}, +{W, 1, "", TV_H_LUMA_0+0x18, 0xb1403480, 0}, +{W, 1, "", TV_H_LUMA_0+0x1c, 0xb1603000, 0}, +{W, 1, "", TV_H_LUMA_0+0x20, 0x2ea03640, 0}, +{W, 1, "", TV_H_LUMA_0+0x24, 0x34002d80, 0}, +{W, 1, "", TV_H_LUMA_0+0x28, 0x3000b120, 0}, +{W, 1, "", TV_H_LUMA_0+0x2c, 0x36e0b160, 0}, +{W, 1, "", TV_H_LUMA_0+0x30, 0x2d202ef0, 0}, +{W, 1, "", TV_H_LUMA_0+0x34, 0xb1203380, 0}, +{W, 1, "", TV_H_LUMA_0+0x38, 0xb1603000, 0}, +{W, 1, "", TV_H_LUMA_0+0x3c, 0x2f303780, 0}, +{W, 1, "", TV_H_LUMA_0+0x40, 0x33002cc0, 0}, +{W, 1, "", TV_H_LUMA_0+0x44, 0x3000b100, 0}, +{W, 1, "", TV_H_LUMA_0+0x48, 0x3820b160, 0}, +{W, 1, "", TV_H_LUMA_0+0x4c, 0x2c802f50, 0}, +{W, 1, "", TV_H_LUMA_0+0x50, 0xb10032a0, 0}, +{W, 1, "", TV_H_LUMA_0+0x54, 0xb1603000, 0}, +{W, 1, "", TV_H_LUMA_0+0x58, 0x2f9038c0, 0}, +{W, 1, "", TV_H_LUMA_0+0x5c, 0x32202c20, 0}, +{W, 1, "", TV_H_LUMA_0+0x60, 0x3000b0e0, 0}, +{W, 1, "", TV_H_LUMA_0+0x64, 0x3980b160, 0}, +{W, 1, "", TV_H_LUMA_0+0x68, 0x2bc02fc0, 0}, +{W, 1, "", TV_H_LUMA_0+0x6c, 0xb0e031c0, 0}, +{W, 1, "", TV_H_LUMA_0+0x70, 0xb1603000, 0}, +{W, 1, "", TV_H_LUMA_0+0x74, 0x2ff03a20, 0}, +{W, 1, "", TV_H_LUMA_0+0x78, 0x31602b60, 0}, +{W, 1, "", TV_H_LUMA_0+0x7c, 0xb020b0c0, 0}, +{W, 1, "", 0x68180, 0x3ae0b160, 0}, +{W, 1, "", 0x68184, 0x2b001810, 0}, +{W, 1, "", 0x68188, 0xb0c03120, 0}, +{W, 1, "", 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0xabb0, 0x00ececec, 0}, +{W, 1, "", 0xabb4, 0x00ededed, 0}, +{W, 1, "", 0xabb8, 0x00eeeeee, 0}, +{W, 1, "", 0xabbc, 0x00efefef, 0}, +{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, +{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, +{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, +{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, +{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, +{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, +{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, +{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, +{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, +{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, +{W, 1, "", 0xabe8, 0x00fafafa, 0}, +{W, 1, "", 0xabec, 0x00fbfbfb, 0}, +{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, +{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, +{W, 1, "", 0xabf8, 0x00fefefe, 0}, +{W, 1, "", 0xabfc, 0x00ffffff, 0}, +{M, 1, "i915 0000:00:02.0:fb0:inteldrmfb frame buffer device", 0x0, 0x0, 0}, +{M, 1, "i915 0000:00:02.0:registered panic notifier", 0x0, 0x0, 0}, +{M, 1, "[drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0", 0x0, 0x0, 0}, +{0,}, +}; + +int niodefs = sizeof (iodefs) / sizeof (iodefs[0]); |