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Diffstat (limited to 'src/mainboard/lenovo/x60')
-rw-r--r--src/mainboard/lenovo/x60/devicetree.cb4
-rw-r--r--src/mainboard/lenovo/x60/romstage.c20
2 files changed, 8 insertions, 16 deletions
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index b3d87ccb4b..1a914fd009 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -76,6 +76,10 @@ chip northbridge/intel/i945
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
+ register "gen1_dec" = "0x007c1601"
+ register "gen2_dec" = "0x000c15e1"
+ register "gen3_dec" = "0x001c1681"
+
device pci 1b.0 on # Audio Controller
subsystemid 0x17aa 0x2010
end
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 34d8d7a435..1008bb0e22 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -33,24 +33,11 @@
#include <southbridge/intel/common/pmclib.h>
#include "dock.h"
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
{
- // Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
- // decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
- | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
- | LPT_LPC_EN | COMA_LPC_EN);
- /* range 0x1600 - 0x167f */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
-
- /* range 0x15e0 - 0x15ef */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
-
- /* range 0x1680 - 0x169f */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
}
static void early_superio_config(void)
@@ -144,7 +131,8 @@ void mainboard_romstage_entry(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */
setup_pch_gpios(&mainboard_gpio_map);
- ich7_enable_lpc();
+ i82801gx_lpc_setup();
+ mb_lpc_decode();
dlpc_init();
/* dock_init initializes the DLPC switch on