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-rw-r--r--src/mainboard/lenovo/t60/romstage.c46
-rw-r--r--src/mainboard/lenovo/x60/romstage.c41
2 files changed, 8 insertions, 79 deletions
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index ac78aae841..ab49e6e979 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -76,9 +76,6 @@ static void rcba_config(void)
RCBA16(D28IR) = 0x7654;
RCBA16(D27IR) = 0x0010;
- /* Enable IOAPIC */
- RCBA8(OIC) = 0x03;
-
/* Disable unused devices */
RCBA32(FD) |= FD_INTLAN;
@@ -89,35 +86,6 @@ static void rcba_config(void)
RCBA64(IOTR3) = 0x000200f0000c0801ULL;
}
-static void early_ich7_init(void)
-{
- uint8_t reg8;
- uint32_t reg32;
-
- // program secondary mlt XXX byte?
- pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
- // reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- reg8 &= ~RTC_BATTERY_DEAD;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
- // usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
- ich7_setup_cir();
-}
-
void mainboard_romstage_entry(void)
{
int s3resume = 0;
@@ -126,15 +94,13 @@ void mainboard_romstage_entry(void)
enable_lapic();
+ /* Set up GPIO's early since it is needed for dock init */
+ i82801gx_setup_bars();
+ setup_pch_gpios(&mainboard_gpio_map);
+
i82801gx_lpc_setup();
mb_lpc_decode();
- /* We want early GPIO setup, to be able to detect legacy I/O module */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
- /* Enable GPIOs */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
- setup_pch_gpios(&mainboard_gpio_map);
-
dock_err = dlpc_init();
/* We prefer Legacy I/O module over docking */
@@ -156,6 +122,7 @@ void mainboard_romstage_entry(void)
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
+ i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
@@ -168,9 +135,6 @@ void mainboard_romstage_entry(void)
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
- /* Perform some initialization that must run before stage2 */
- early_ich7_init();
-
/* This should probably go away. Until now it is required
* and mainboard specific
*/
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1008bb0e22..6eeb2d12ba 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -77,9 +77,6 @@ static void rcba_config(void)
RCBA16(D28IR) = 0x7654;
RCBA16(D27IR) = 0x0010;
- /* Enable IOAPIC */
- RCBA8(OIC) = 0x03;
-
/* Disable unused devices */
RCBA32(FD) |= FD_INTLAN;
@@ -90,35 +87,6 @@ static void rcba_config(void)
RCBA64(IOTR3) = 0x000200f0000c0801ULL;
}
-static void early_ich7_init(void)
-{
- uint8_t reg8;
- uint32_t reg32;
-
- // program secondary mlt XXX byte?
- pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);
-
- // reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- reg8 &= ~RTC_BATTERY_DEAD;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
-
- // usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
- reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
- reg32 |= (1 << 29) | (1 << 17);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
-
- reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
- reg32 |= (1 << 31) | (1 << 27);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
-
- ich7_setup_cir();
-}
-
void mainboard_romstage_entry(void)
{
int s3resume = 0;
@@ -126,9 +94,8 @@ void mainboard_romstage_entry(void)
enable_lapic();
- /* Enable GPIOs */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */
+ /* Set up GPIO's early since it is needed for dock init */
+ i82801gx_setup_bars();
setup_pch_gpios(&mainboard_gpio_map);
i82801gx_lpc_setup();
@@ -161,6 +128,7 @@ void mainboard_romstage_entry(void)
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
+ i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
@@ -173,9 +141,6 @@ void mainboard_romstage_entry(void)
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
- /* Perform some initialization that must run before stage2 */
- early_ich7_init();
-
/* This should probably go away. Until now it is required
* and mainboard specific
*/