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-rw-r--r--src/mainboard/lenovo/t60/romstage.c9
-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c4
-rw-r--r--src/mainboard/lenovo/x201/romstage.c10
-rw-r--r--src/mainboard/lenovo/x60/romstage.c9
-rw-r--r--src/mainboard/lenovo/z61t/romstage.c9
5 files changed, 9 insertions, 32 deletions
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 2817023fcd..243e16112e 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -24,7 +24,6 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
@@ -157,14 +156,13 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
int s3resume = 0;
int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0)
- enable_lapic();
+ enable_lapic();
ich7_enable_lpc();
@@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Setup the console */
console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset();
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index e41035166c..bbb73dd57c 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <device/pci_ops.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
@@ -60,7 +59,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -74,7 +73,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
- report_bist_failure(bist);
enable_smbus();
x4x_early_init();
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 73f5bccf92..067528b87b 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -23,7 +23,6 @@
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h>
#include <timestamp.h>
@@ -167,14 +166,12 @@ static void set_fsb_frequency(void)
smbus_block_write(0x69, 0, 5, block);
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
u32 reg32;
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
-
- if (bist == 0)
- enable_lapic();
+ enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE);
@@ -197,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 590e7864b4..2b8a9badba 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
@@ -157,13 +156,12 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0)
- enable_lapic();
+ enable_lapic();
/* Enable GPIOs */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
@@ -190,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist)
else
printk(BIOS_DEBUG, "Dock is not present\n");
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n");
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 4c487c0df5..8946179c4a 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -24,7 +24,6 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
@@ -157,14 +156,13 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
{
int s3resume = 0;
int dock_err;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0)
- enable_lapic();
+ enable_lapic();
ich7_enable_lpc();
@@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Setup the console */
console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
system_reset();