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-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c39
1 files changed, 6 insertions, 33 deletions
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 8be2c86734..5594cbdda6 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -15,45 +15,18 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
-#include <arch/romstage.h>
-#include <device/pci_ops.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-void mainboard_romstage_entry(void)
+void mb_lpc_setup(void)
{
- // ch0 ch1
- const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
- u8 boot_path = 0;
- u8 s3_resume;
-
- /* Set southbridge and Super I/O GPIOs. */
- i82801gx_lpc_setup();
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
- console_init();
-
- enable_smbus();
-
- i82801gx_early_init();
- x4x_early_init();
-
- s3_resume = southbridge_detect_s3_resume();
- if (s3_resume)
- boot_path = BOOT_PATH_RESUME;
- if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
- boot_path = BOOT_PATH_WARM_RESET;
-
- sdram_initialize(boot_path, spd_addrmap);
-
- x4x_late_init(s3_resume);
-
- printk(BIOS_DEBUG, "x4x late init complete\n");
-
+void mb_get_spd_map(u8 spd_map[4])
+{
+ spd_map[0] = 0x50;
+ spd_map[2] = 0x52;
}