diff options
Diffstat (limited to 'src/mainboard/lippert/frontrunner/romstage.c')
| -rw-r--r-- | src/mainboard/lippert/frontrunner/romstage.c | 71 |
1 files changed, 49 insertions, 22 deletions
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index df301fcadd..6630b581d8 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -1,4 +1,5 @@ #include <stdint.h> +#include <spd.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> @@ -15,35 +16,61 @@ #include "southbridge/amd/cs5535/cs5535_early_smbus.c" #include "southbridge/amd/cs5535/cs5535_early_setup.c" -#include "northbridge/amd/gx2/raminit.h" -/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */ + 0xFF, 0xFF, /* only values used by raminit.c are set */ + [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */ + [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */ + [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */ + [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */ + 0xFF, 0xFF, 0xFF, + [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */ + 0xFF, 0xFF, + [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */ + [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */ + 0xFF, 0xFF, 0xFF, + [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */ + [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */ + 0xFF, 0xFF, + [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */ + [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */ + [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */ + 0xFF, + [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */ + 0xFF, + [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */ + [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */ + [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */ + [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */ + [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */ +}; + +static inline int spd_read_byte(unsigned int device, unsigned int address) { - msr_t msr; - /* 1. Initialize GLMC registers base on SPD values, - * Hard coded as XpressROM for now */ - //print_debug("sdram_enable step 1\n"); - msr = rdmsr(0x20000018); - msr.hi = 0x10076013; - msr.lo = 0x3400; - wrmsr(0x20000018, msr); - - msr = rdmsr(0x20000019); - msr.hi = 0x18000008; - msr.lo = 0x696332a3; - wrmsr(0x20000019, msr); + if (device != DIMM0) + return 0xFF; /* No DIMM1, don't even try. */ + +#if CONFIG_DEBUG_SMBUS + if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { + print_err("ERROR: spd_read_byte(DIMM0, 0x"); + print_err_hex8(address); + print_err(") returns 0xff\n"); + } +#endif + /* Fake SPD ROM value */ + return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; } +#include "northbridge/amd/gx2/raminit.h" +#include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" - -#define PLLMSRhi 0x00000226 -#define PLLMSRlo 0x00000008 -#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) -#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) -#include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c" |