13 files changed, 367 insertions, 0 deletions
diff --git a/src/mainboard/lowrisc/Kconfig b/src/mainboard/lowrisc/Kconfig
new file mode 100644
index 0000000000..ba0fbe7499
--- /dev/null
+++ b/src/mainboard/lowrisc/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_LOWRISC
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/lowrisc/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/lowrisc/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "lowrisc"
+
+endif # VENDOR_LOWRISC
diff --git a/src/mainboard/lowrisc/Kconfig.name b/src/mainboard/lowrisc/Kconfig.name
new file mode 100644
index 0000000000..4c992fc2bb
--- /dev/null
+++ b/src/mainboard/lowrisc/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_LOWRISC
+	bool "lowrisc"
diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig
new file mode 100644
index 0000000000..f0a3637d1c
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+if BOARD_LOWRISC_NEXYS4DDR
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SOC_LOWRISC_LOWRISC
+	select BOARD_ROMSIZE_KB_4096
+	select DRIVERS_UART_8250MEM
+	select BOOT_DEVICE_NOT_SPI_FLASH
+	select UART_OVERRIDE_REFCLK
+	select UART_OVERRIDE_INPUT_CLOCK_DIVIDER
+
+config MAINBOARD_DIR
+	string
+	default lowrisc/nexys4ddr
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "LOWRISC NEXYS4DDR"
+
+config MAX_CPUS
+	int
+	default 1
+
+endif #  BOARD_LOWRISC_NEXYS4DDR
diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig.name b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name
new file mode 100644
index 0000000000..f99b3cc649
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LOWRISC_NEXYS4DDR
+	bool "nexys4ddr"
diff --git a/src/mainboard/lowrisc/nexys4ddr/Makefile.inc b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc
new file mode 100644
index 0000000000..69519b189e
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+bootblock-y += uart.c
+bootblock-y += util.c
+bootblock-y += rom_media.c
+romstage-y += romstage.c
+romstage-y += uart.c
+romstage-y += util.c
+romstage-y += rom_media.c
+ramstage-y += uart.c
+ramstage-y += util.c
+ramstage-y += rom_media.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/lowrisc/nexys4ddr/board_info.txt b/src/mainboard/lowrisc/nexys4ddr/board_info.txt
new file mode 100644
index 0000000000..a305030ddb
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/board_info.txt
@@ -0,0 +1,3 @@
+Board name: lowrisc nexys4ddr
+Category: eval
+Board URL: https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&oq=Tutorial+for+the+debug+preview+of+lowRISC&btnI
diff --git a/src/mainboard/lowrisc/nexys4ddr/devicetree.cb b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb
new file mode 100644
index 0000000000..e857276d5f
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/devicetree.cb
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Google, Inc.
+##
+## This software is licensed under the terms of the GNU General Public
+## License version 2, as published by the Free Software Foundation, and
+## may be copied, distributed, and modified under those terms.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+
+chip soc/ucb/riscv
+	device cpu_cluster 0 on end
+	chip drivers/generic/generic # I2C0 controller
+		device i2c 6 on end # Fake component for testing
+	end
+end
diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c
new file mode 100644
index 0000000000..b2ce39886c
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <symbols.h>
+
+static void mainboard_enable(device_t dev)
+{
+	/*
+	 * TODO: Get this size from the hardware-supplied configuration string.
+	 */
+	const size_t ram_size = 1*GiB;
+
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
new file mode 100644
index 0000000000..0348c47366
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+#define START 0x80000000
+
+SECTIONS
+{
+	DRAM_START(START)
+	BOOTBLOCK(START, 64K)
+	STACK(START + 8M, 64K)
+	ROMSTAGE(START + 8M + 64K, 128K)
+	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
+	PAGETABLES(START + 8M + 200K, 56K)
+	RAMSTAGE(START + 8M + 256K, 256K)
+}
diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c
new file mode 100644
index 0000000000..7d4ed00fe1
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <boot_device.h>
+#include <symbols.h>
+
+/*
+ * _dram is the start of RAM. We currently need to load coreboot.rom into
+ * RAM. The actual "rom" code on the FPGAs is in a block ram.
+ */
+static const struct mem_region_device boot_dev =
+	MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &boot_dev.rdev;
+}
diff --git a/src/mainboard/lowrisc/nexys4ddr/romstage.c b/src/mainboard/lowrisc/nexys4ddr/romstage.c
new file mode 100644
index 0000000000..1509efb0f1
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <program_loading.h>
+#include <console/console.h>
+
+void main(void)
+{
+	console_init();
+	run_ramstage();
+}
diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c
new file mode 100644
index 0000000000..e3c233f80b
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/uart.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <spike_util.h>
+
+uintptr_t uart_platform_base(int idx)
+{
+	return (uintptr_t) 0x42000000;
+}
+
+/* these are currently not quite right but they are here for reference
+ * and will be fixed when lowrisc gives us a standard clock
+ * and set of values. */
+// divisor = clk_freq / (16 * Baud)
+unsigned int uart_input_clock_divider(void)
+{
+	return (25 * 1000 * 1000u / (16u * 115200u)) % 0x100;
+}
+
+// System clock 25 MHz, 115200 baud rate
+unsigned int uart_platform_refclk(void)
+{
+	return (25 * 1000 * 1000u / (16u * 115200u)) >> 8;
+}
diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c
new file mode 100644
index 0000000000..32cdb6d573
--- /dev/null
+++ b/src/mainboard/lowrisc/nexys4ddr/util.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2013, The Regents of the University of California (Regents).
+ * All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Regents nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT,
+ * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING
+ * LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS
+ * DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING
+ * DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS
+ * IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT,
+ * UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ */
+
+#include <arch/barrier.h>
+#include <arch/errno.h>
+#include <atomic.h>
+#include <console/console.h>
+#include <spike_util.h>
+#include <string.h>
+#include <vm.h>
+
+uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info)
+{
+	if (id == 0) {
+		mprv_write_ulong(&info->base, 2U*GiB);
+
+		/* TODO: Return the correct value */
+		mprv_write_ulong(&info->size, 1*GiB);
+		return 0;
+	}
+
+	return -1;
+}
+
+uintptr_t mcall_send_ipi(uintptr_t recipient)
+{
+	die("mcall_send_ipi is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_clear_ipi(void)
+{
+	// only clear SSIP if no other events are pending
+	if (HLS()->device_response_queue_head == NULL) {
+		clear_csr(mip, MIP_SSIP);
+		/* Ensure the other hart sees it. */
+		mb();
+	}
+
+	return atomic_swap(&HLS()->ipi_pending, 0);
+}
+
+uintptr_t mcall_shutdown(void)
+{
+	die("mcall_shutdown is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_set_timer(unsigned long long when)
+{
+	printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n");
+	return 0;
+}
+
+uintptr_t mcall_dev_req(sbi_device_message *m)
+{
+	die("mcall_dev_req is currently not implemented");
+	return 0;
+}
+
+uintptr_t mcall_dev_resp(void)
+{
+	die("mcall_dev_resp is currently not implemented");
+	return 0;
+}
+
+void hls_init(uint32_t hart_id)
+{
+	memset(HLS(), 0, sizeof(*HLS()));
+	HLS()->hart_id = hart_id;
+}
+
+uintptr_t mcall_console_putchar(uint8_t ch)
+{
+	do_putchar(ch);
+	return 0;
+}