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+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if USE_FAILOVER_IMAGE
+ default ROM_SECTION_SIZE = FAILOVER_SIZE
+ default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
+else
+ if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
+ else
+ default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
+ default ROM_SECTION_OFFSET = 0
+ end
+end
+
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 65536
+
+if USE_FAILOVER_IMAGE
+ default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+ if USE_FALLBACK_IMAGE
+ default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+ else
+ default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+ end
+end
+
+arch i386 end
+
+driver mainboard.o
+object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+# object reset.o
+
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ makerule ./cache_as_ram_auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ end
+ else
+ makerule ./cache_as_ram_auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ end
+ end
+end
+
+if USE_FAILOVER_IMAGE
+else
+ if CONFIG_AP_CODE_IN_CAR
+ makerule ./apc_auto.o
+ depends "$(MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ end
+ ldscript /arch/i386/init/ldscript_apc.lb
+ end
+end
+
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+end
+
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+end
+
+mainboardinit southbridge/nvidia/mcp55/id.inc
+ldscript /southbridge/nvidia/mcp55/id.lds
+
+# ROMSTRAP table for MCP55.
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+ ldscript /southbridge/nvidia/mcp55/romstrap.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit southbridge/nvidia/mcp55/romstrap.inc
+ ldscript /southbridge/nvidia/mcp55/romstrap.lds
+ end
+end
+
+if USE_DCACHE_RAM
+ mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover_failover.lds
+ end
+ end
+else
+ if USE_FALLBACK_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+ end
+ end
+end
+
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ initobject cache_as_ram_auto.o
+ else
+ mainboardinit ./cache_as_ram_auto.inc
+ end
+end
+
+if CONFIG_CHIP_NAME
+ config chip.h
+end
+
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_AM2 # CPU
+ device apic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # Northbridge / mc0
+ device pci 18.0 on
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/mcp55 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627ehg # Super I/O
+ device pnp 4e.5 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.6 off # Com2 / IrDA
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.7 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.8 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.b on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 4e.c on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ end
+ end
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ # TODO: Needed?
+ # chip drivers/generic/generic # DIMM 1-0-0
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-0-1
+ # device i2c 55 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-0
+ # device i2c 56 on end
+ # end
+ # chip drivers/generic/generic # DIMM 1-1-1
+ # device i2c 57 on end
+ # end
+ end
+ # TODO: Check if the stuff below is correct / needed.
+ device pci 1.1 on # SM 1
+ # PCI device SMBus address will depend on addon PCI device,
+ # do we need to scan_smbus_bus?
+
+ # chip drivers/generic/generic # PCIXA Slot1
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic # PCIXB Slot1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic # PCIXB Slot2
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic # PCI Slot1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic # Master MCP55 PCI-E
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic # Slave MCP55 PCI-E
+ # device i2c 55 on end
+ # end
+ chip drivers/generic/generic # MAC EEPROM
+ device i2c 51 on end
+ end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 on end # IDE
+ device pci 5.0 on end # SATA 0
+ device pci 5.1 on end # SATA 1
+ device pci 5.2 off end # SATA 2 (N/A on this board)
+ device pci 6.0 on end # PCI
+ device pci 6.1 on end # AZA (HD Audio)
+ device pci 8.0 on end # NIC
+ device pci 9.0 off end # NIC (N/A on this board)
+ device pci a.0 off end # PCI E 5 (N/A on this board?)
+ device pci b.0 on end # PCI E 4
+ device pci c.0 on end # PCI E 3
+ device pci d.0 on end # PCI E 2
+ device pci e.0 on end # PCI E 1
+ device pci f.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # TODO: Check the two lines below.
+ register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
+ register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.0 on end # Link 1
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+
+# TODO
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 on end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 on end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # io
+# device pnp 0.9 off end # io
+# end
+
+end