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-rw-r--r--src/mainboard/msi/ms7260/romstage.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index b37cd1f4bf..13dd4049b4 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -42,6 +42,7 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <lib.h>
+#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
- (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
- (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// Node 1
- (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
- (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE