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-rw-r--r--src/mainboard/msi/ms7721/OemCustomize.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index a5e2a4c5b4..3c8d5c51b2 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -68,57 +68,57 @@
* 38 DP2_TX[P,N]6
*/
-static const PCIe_PORT_DESCRIPTOR PortList [] = {
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
};
-static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// DP0 to HDMI0/DP
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
},
// DP1 to FCH
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
},
// DP2 to HDMI1/DP
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
},
};
@@ -218,14 +218,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/
PSO_END
};