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Diffstat (limited to 'src/mainboard/msi/ms9282')
| -rw-r--r-- | src/mainboard/msi/ms9282/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index fd9049146a..4fa40bf0ce 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); //wait_all_other_cores_started(bsp_apicid); |