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-rw-r--r--src/mainboard/msi/ms7260/romstage.c15
-rw-r--r--src/mainboard/msi/ms9185/romstage.c4
-rw-r--r--src/mainboard/msi/ms9282/romstage.c15
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c43
4 files changed, 57 insertions, 20 deletions
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index b3f9d4ef62..5b036d6631 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -38,10 +38,22 @@
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+unsigned get_sbdn(unsigned bus);
+
+unsigned get_sbdn(unsigned bus)
+{
+ pci_devfn_t dev;
+
+ /* Find the device. */
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
+
+ return (dev >> 15) & 0x1f;
+}
+
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@@ -50,6 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 6f5ff3202c..db5242926a 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -39,11 +39,12 @@
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
+unsigned get_sbdn(unsigned bus);
+
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -60,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
+#include "southbridge/broadcom/bcm5785/early_setup.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 7d360e3790..2dd1283bc7 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -39,10 +39,22 @@
#include <spd.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <device/pci_ids.h>
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+unsigned get_sbdn(unsigned bus);
+
+unsigned get_sbdn(unsigned bus)
+{
+ pci_devfn_t dev;
+
+ /* Find the device. */
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
+
+ return (dev >> 15) & 0x1f;
+}
+
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -59,6 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index e22ec11b94..7e987a01b9 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -30,33 +30,46 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/early_smbus.c"
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdfam10/reset_test.c"
+#include <cpu/amd/car.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdfam10/debug.c"
-#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdht/ht_wrapper.h>
+#include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <arch/early_variables.h>
+#include <cbmem.h>
+#include "southbridge/nvidia/mcp55/early_smbus.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
+void activate_spd_rom(const struct mem_controller *ctrl);
+int spd_read_byte(unsigned device, unsigned address);
+extern struct sys_info sysinfo_car;
+
+void activate_spd_rom(const struct mem_controller *ctrl) { }
-static inline int spd_read_byte(unsigned device, unsigned address)
+inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-#include <northbridge/amd/amdfam10/amdfam10.h>
-#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/pci.c"
-#include "resourcemap.c"
-#include "cpu/amd/quadcore/quadcore.c"
+unsigned get_sbdn(unsigned bus)
+{
+ pci_devfn_t dev;
+
+ /* Find the device. */
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
+
+ return (dev >> 15) & 0x1f;
+}
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
@@ -68,10 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include <cpu/amd/microcode.h>
-
-#include "cpu/amd/family_10h-family_15h/init_cpus.c"
-#include "northbridge/amd/amdfam10/early_ht.c"
static void sio_setup(void)
{