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-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 7848e9e95c..8538d33a50 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <delay.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/msr.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <cpu/x86/bist.h>
@@ -190,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
#if IS_ENABLED(CONFIG_SET_FIDVID)
- msr = rdmsr(0xc0010071);
+ msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
@@ -208,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr = rdmsr(0xc0010071);
+ msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
init_timer(); /* Need to use TMICT to synchronize FID/VID. */