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-rw-r--r--src/mainboard/msi/ms6119/romstage.c4
-rw-r--r--src/mainboard/msi/ms6147/romstage.c4
-rw-r--r--src/mainboard/msi/ms6156/romstage.c4
3 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c
index aaa03ee52d..5dde6c4e55 100644
--- a/src/mainboard/msi/ms6119/romstage.c
+++ b/src/mainboard/msi/ms6119/romstage.c
@@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
- /* Enable access to the full ROM chip, needed very early by CBFS. */
- i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
enable_smbus();
dump_spd_registers();
sdram_set_registers();
diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c
index 2f84fbffd6..dfa9c993ae 100644
--- a/src/mainboard/msi/ms6147/romstage.c
+++ b/src/mainboard/msi/ms6147/romstage.c
@@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
- /* Enable access to the full ROM chip, needed very early by CBFS. */
- i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
enable_smbus();
dump_spd_registers();
sdram_set_registers();
diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index 45c97eea6a..4e25f093b7 100644
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -26,7 +26,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
console_init();
report_bist_failure(bist);
- /* Enable access to the full ROM chip, needed very early by CBFS. */
- i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
enable_smbus();
dump_spd_registers();
sdram_set_registers();