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-rw-r--r--src/mainboard/nvidia/l1_2pvv/Kconfig6
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c4
2 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 1a260bf8e0..06e10ab92a 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
@@ -44,6 +46,10 @@ config MEM_TRAIN_SEQ
int
default 1
+config MCP55_NUM
+ int
+ default 2
+
config SB_HT_CHAIN_ON_BUS0
int
default 2
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index dc76e0a32e..fc135d8378 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -100,10 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 2
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 2
#define MCP55_PCI_E_X_1 4