diff options
Diffstat (limited to 'src/mainboard/ocp/wedge100s/romstage.c')
| -rw-r--r-- | src/mainboard/ocp/wedge100s/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index b8da280e9b..7fdc981915 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -38,7 +38,7 @@ void early_mainboard_romstage_entry(void) pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1); - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -76,7 +76,7 @@ void late_mainboard_romstage_entry(void) void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr; - if (IS_ENABLED(CONFIG_FSP_USES_UPD)) { + if (CONFIG(FSP_USES_UPD)) { /* The internal UART operates on 0x3f8/0x2f8. * As it's not wired up and conflicts with SuperIO decoding * the same range, make sure to disable it. @@ -91,7 +91,7 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) fsp_upd_data->SerialPortBaudRate = 0; /* Make FSP use serial IO */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) fsp_upd_data->SerialPortType = 1; else fsp_upd_data->SerialPortType = 0; |