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-rw-r--r--src/mainboard/pcengines/apu2/romstage.c16
1 files changed, 4 insertions, 12 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index c95adb6555..1ccf7c4e36 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -52,8 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -85,27 +84,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
init_tpm(false);
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
-
static void early_lpc_init(void)
{
u32 setting = 0x0;