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-rw-r--r--src/mainboard/pcengines/apu1/mainboard.c2
-rw-r--r--src/mainboard/pcengines/apu1/mptable.c2
-rw-r--r--src/mainboard/pcengines/apu2/mptable.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 290a0ed231..de949371fa 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -91,7 +91,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
*/
/*
* The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because of PCI INT_PIN swizzle isnt implemented to match
+ * but because of PCI INT_PIN swizzle isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
index b183d8de24..94a7d6fb70 100644
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ b/src/mainboard/pcengines/apu1/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index dff5fbda14..772ee31734 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_isa;
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);