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-rw-r--r--src/mainboard/rca/rm4100/Kconfig22
-rw-r--r--src/mainboard/rca/rm4100/Makefile.inc2
-rw-r--r--src/mainboard/rca/rm4100/devicetree.cb2
-rw-r--r--src/mainboard/rca/rm4100/romstage.c6
4 files changed, 21 insertions, 11 deletions
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
index fb3ab625e1..7464f887e2 100644
--- a/src/mainboard/rca/rm4100/Kconfig
+++ b/src/mainboard/rca/rm4100/Kconfig
@@ -1,18 +1,20 @@
config BOARD_RCA_RM4100
bool "RM4100"
select ARCH_X86
- select CPU_INTEL_SOCKET_PGA370
+ select CPU_INTEL_SOCKET_MFCBGA479
select NORTHBRIDGE_INTEL_I82830
select SOUTHBRIDGE_INTEL_I82801DX
select SUPERIO_SMSC_SMSCSUPERIO
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
- select BOARD_ROMSIZE_KB_1024
- select HAVE_MAINBOARD_RESOURCES
+ select BOARD_ROMSIZE_KB_1024
select HAVE_HARD_RESET
+ select HAVE_MAINBOARD_RESOURCES
+ select USE_PRINTK_IN_CAR
select HAVE_SMI_HANDLER
- select GFXUMA
+ select GFXUMA
+ select USE_DCACHE_RAM
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -29,6 +31,16 @@ config HAVE_OPTION_TABLE
default n
depends on BOARD_RCA_RM4100
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+ depends on BOARD_RCA_RM4100
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_RCA_RM4100
+
config IRQ_SLOT_COUNT
int
default 7
diff --git a/src/mainboard/rca/rm4100/Makefile.inc b/src/mainboard/rca/rm4100/Makefile.inc
index 38a5a61fdd..6c034c0e1f 100644
--- a/src/mainboard/rca/rm4100/Makefile.inc
+++ b/src/mainboard/rca/rm4100/Makefile.inc
@@ -1,4 +1,2 @@
-ROMCCFLAGS=-mcpu=p3 -O
-
smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
index 4dff3bea53..bf2cee082a 100644
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ b/src/mainboard/rca/rm4100/devicetree.cb
@@ -1,6 +1,6 @@
chip northbridge/intel/i82830 # Northbridge
device apic_cluster 0 on # APIC cluster
- chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479
+ chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479
device apic 0 on end # APIC
end
end
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index b1bc4b4d1a..c93cec6b37 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -34,7 +34,6 @@
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_reset.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
@@ -98,10 +97,11 @@ static void mb_early_setup(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
-static void main(unsigned long bist)
+#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
+
+void real_main(unsigned long bist)
{
if (bist == 0) {
- early_mtrr_init();
if (memory_initialized()) {
hard_reset();
}