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-rw-r--r--src/mainboard/roda/rk886ex/romstage.c5
-rw-r--r--src/mainboard/roda/rk9/romstage.c5
2 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 1b16266c43..0003401508 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -23,7 +23,6 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
-#include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@ -210,10 +209,6 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
if (bist == 0)
enable_lapic();
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 1bcfd622f0..b88671c705 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -30,7 +30,6 @@
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include <superio/smsc/lpc47n227/lpc47n227.h>
-#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
@@ -107,7 +106,6 @@ static void default_superio_gpio_setup(void)
/* Exit configuration state. */
pnp_exit_conf_state(sio);
-
/* Enable decoding of 0x600-0x60f through lpc. */
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
@@ -123,9 +121,6 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();