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-rw-r--r--src/mainboard/samsung/lumpy/chromeos.c26
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c27
2 files changed, 12 insertions, 41 deletions
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 6760f03611..9e02d9a901 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <bootmode.h>
+#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,15 +30,13 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE
-#include <boot/coreboot_tables.h>
#include "ec.h"
#include <ec/smsc/mec1308/ec.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
- struct device *dev = pcidev_on_root(0x1f, 0);
- u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
u8 lid = ec_read(0x83);
struct lb_gpio chromeos_gpios[] = {
@@ -60,36 +59,23 @@ void fill_lb_gpios(struct lb_gpios *gpios)
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
-#endif
int get_write_protect_state(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
if (get_gpio(GPIO_SPI_WP))
@@ -98,7 +84,7 @@ void init_bootmode_straps(void)
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags);
+ pci_s_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 9ec4218b01..f316b2256f 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <bootmode.h>
+#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
@@ -28,13 +29,10 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE
-#include <boot/coreboot_tables.h>
-
void fill_lb_gpios(struct lb_gpios *gpios)
{
- struct device *dev = pcidev_on_root(0x1f, 0);
- u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO68 = CHP3_SPI_WP */
@@ -57,36 +55,23 @@ void fill_lb_gpios(struct lb_gpios *gpios)
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
-#endif
int get_write_protect_state(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))
@@ -95,7 +80,7 @@ void init_bootmode_straps(void)
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags);
+ pci_s_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {