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-rw-r--r--src/mainboard/sapphire/pureplatinumh61/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index 95c59dfca3..aff01302b2 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x000c0a01"
register "gen3_dec" = "0x00000000"
register "gen4_dec" = "0x00000000"
- register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"