diff options
Diffstat (limited to 'src/mainboard/siemens/chili/variants/base')
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/board_info.txt | 1 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/data.vbt | bin | 0 -> 6144 bytes | |||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/devicetree.cb | 136 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/gma-mainboard.ads | 19 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/gpio.c | 129 |
6 files changed, 290 insertions, 0 deletions
diff --git a/src/mainboard/siemens/chili/variants/base/Makefile.inc b/src/mainboard/siemens/chili/variants/base/Makefile.inc new file mode 100644 index 0000000000..86b9433353 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/siemens/chili/variants/base/board_info.txt b/src/mainboard/siemens/chili/variants/base/board_info.txt new file mode 100644 index 0000000000..a5d0991f51 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/board_info.txt @@ -0,0 +1 @@ +Board name: Chili base board diff --git a/src/mainboard/siemens/chili/variants/base/data.vbt b/src/mainboard/siemens/chili/variants/base/data.vbt Binary files differnew file mode 100644 index 0000000000..f79a600525 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/data.vbt diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb new file mode 100644 index 0000000000..505e9a4852 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/cannonlake + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "0" + register "speed_shift_enable" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 off end # PCIe x16 + device pci 01.1 off end # PCIe x8 + device pci 01.2 off end # PCIe x4 + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 05.0 off end # Imaging Processing Unit + device pci 08.0 off end # Gaussian mixture model, Neural network accelerator + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # ISH + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # SIMATIC NET CP 5711 + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" # upper blue + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" # lower blue + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # STM SC? + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C? + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # upper blue + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" # lower blue + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi Wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" # HDD / SSD + register "SataPortsEnable[1]" = "1" # ODD + register "SataPortsEnable[3]" = "1" # HDD / SSD + + register "SataPortsDevSlp[0]" = "1" # M.2 + register "SataPortsDevSlp[2]" = "1" # HDD / SSD + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 i219 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcUsage[4]" = "0x70" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[4]" = "0" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 i210 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[5]" = "5" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[5]" = "0" + end + device pci 1c.6 on # PCI Express Port 7 + device pci 00.0 on end # x1 M.2 (WLAN / BT) + register "PcieRpEnable[6]" = "1" + register "PcieRpSlotImplemented[6]" = "1" + end + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on # PCI Express Port 17 + device pci 00.0 on end # x4 M.2/M + register "PcieRpEnable[16]" = "1" + register "PcieClkSrcUsage[7]" = "16" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieRpSlotImplemented[16]" = "1" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + device pci 1f.7 off end # TraceHub + end +end diff --git a/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads new file mode 100644 index 0000000000..42a2f2cea4 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- VGA (DVI-I) + HDMI2, -- DVI-I + DP3, -- DP++ + HDMI3, -- DP++ + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c new file mode 100644 index 0000000000..65ea037a3a --- /dev/null +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "variant.h" + +static const struct pad_config gpio_table[] = { +/* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), +/* GPP_A16 GPIO */ PAD_NC(GPP_A16, DN_20K), +/* GPP_B4 GPIO */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* GPP_B5 GPIO */ PAD_NC(GPP_B5, NONE), +/* GPP_B6 GPIO */ PAD_NC(GPP_B6, NONE), +/* GPP_B8 GPIO */ PAD_NC(GPP_B8, NONE), +/* GPP_B10 GPIO */ PAD_NC(GPP_B10, NONE), +/* GPP_B11 GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), +/* GPP_B14 SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GPP_B18 GPIO */ PAD_NC(GPP_B18, NONE), +/* GPP_B22 GPIO */ PAD_NC(GPP_B22, NONE), +/* GPP_C2 GPIO */ PAD_NC(GPP_C2, NONE), +/* GPP_C5 GPIO */ PAD_NC(GPP_C5, NONE), +/* GPP_C6 SML1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* GPP_C7 SML1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* GPP_C8 GPIO */ PAD_NC(GPP_C8, NONE), +/* GPP_C9 GPIO */ PAD_NC(GPP_C9, NONE), +/* GPP_C12 GPIO */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* GPP_C13 GPIO */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* GPP_C14 GPIO */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* GPP_C15 GPIO */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* GPP_C16 I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), +/* GPP_C17 I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* GPP_C22 UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* GPP_C23 UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* GPP_D1 GPIO */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), +/* GPP_D2 GPIO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), +/* GPP_D3 GPIO */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* GPP_D7 GPIO */ PAD_CFG_GPI(GPP_D7, NONE, PLTRST), +/* GPP_D8 GPIO */ PAD_CFG_GPI(GPP_D8, NONE, PLTRST), +/* GPP_D17 DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* GPP_D18 DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* GPP_D19 DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* GPP_D20 DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* GPP_D21 GPIO */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* GPP_D22 GPIO */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), +/* GPP_G1 GPIO */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* GPP_G2 GPIO */ PAD_CFG_GPI(GPP_G2, NONE, PLTRST), +/* GPP_G3 GPIO */ PAD_CFG_GPI_APIC(GPP_G3, NONE, DEEP, LEVEL, INVERT), +/* I2S1_SFRM GPIO */ PAD_NC(I2S1_SFRM, NONE), +/* I2S1_TXD GPIO */ PAD_NC(I2S1_TXD, NONE), +/* GPD0 BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* GPD1 ACPRESENT */ PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), +/* GPD7 GPIO */ PAD_CFG_GPO(GPD7, 0, RSMRST), +/* GPP_K0 GPIO */ PAD_CFG_GPI(GPP_K0, NONE, PLTRST), +/* GPP_K1 GPIO */ PAD_CFG_GPI(GPP_K1, NONE, PLTRST), +/* GPP_K2 GPIO */ PAD_CFG_GPI(GPP_K2, NONE, PLTRST), +/* GPP_K3 GPIO */ PAD_CFG_GPI(GPP_K3, NONE, PLTRST), +/* GPP_K4 GPIO */ PAD_CFG_GPO(GPP_K4, 1, PWROK), +/* GPP_K5 GPIO */ PAD_CFG_GPO(GPP_K5, 1, PWROK), +/* GPP_K8 GPIO */ PAD_NC(GPP_K8, NONE), +/* GPP_K9 GPIO */ PAD_NC(GPP_K9, NONE), +/* GPP_K10 GPIO */ PAD_NC(GPP_K10, NONE), +/* GPP_K11 GPIO */ PAD_NC(GPP_K11, NONE), +/* GPP_K20 GPIO */ PAD_CFG_GPO(GPP_K20, 1, PLTRST), +/* GPP_K21 GPIO */ PAD_NC(GPP_K21, NONE), +/* GPP_H0 GPIO */ PAD_CFG_GPI(GPP_H0, NONE, PLTRST), +/* GPP_H2 GPIO */ PAD_NC(GPP_H2, NONE), +/* GPP_H3 GPIO */ PAD_NC(GPP_H3, NONE), +/* GPP_H10 GPIO */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* GPP_H15 GPIO */ PAD_CFG_GPO(GPP_H15, 1, DEEP), +/* GPP_H17 GPIO */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* GPP_E0 SATAXPCIE0 */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* GPP_E1 GPIO */ PAD_NC(GPP_E1, NONE), +/* GPP_E2 GPIO */ PAD_NC(GPP_E2, NONE), +/* GPP_E4 SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* GPP_E5 GPIO */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), +/* GPP_E6 GPIO */ PAD_CFG_GPI(GPP_E6, NONE, DEEP), +/* GPP_E8 SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* GPP_E9 USB2_OC0# */ PAD_CFG_NF(GPP_E9, UP_20K, DEEP, NF1), +/* GPP_E10 USB2_OC1# */ PAD_CFG_NF(GPP_E10, UP_20K, DEEP, NF1), +/* GPP_E11 USB2_OC2# */ PAD_CFG_NF(GPP_E11, UP_20K, DEEP, NF1), +/* GPP_E12 GPIO */ PAD_CFG_GPO(GPP_E12, 1, PLTRST), +/* GPP_F1 GPIO */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 GPIO */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 GPIO */ PAD_NC(GPP_F3, NONE), +/* GPP_F4 GPIO */ PAD_NC(GPP_F4, NONE), +/* GPP_F5 GPIO */ PAD_CFG_GPO(GPP_F5, 1, PLTRST), +/* GPP_F6 SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* GPP_F8 GPIO */ PAD_CFG_GPO(GPP_F8, 0, DEEP), +/* GPP_F9 GPIO */ PAD_CFG_GPO(GPP_F9, 0, DEEP), +/* GPP_F10 GPIO */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), +/* GPP_F13 GPIO */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* GPP_F14 GPIO */ PAD_NC(GPP_F14, NONE), +/* GPP_F15 USB2_OC4# */ PAD_CFG_NF(GPP_F15, UP_20K, DEEP, NF1), +/* GPP_F16 USB2_OC5# */ PAD_CFG_NF(GPP_F16, UP_20K, DEEP, NF1), +/* GPP_F17 USB2_OC6# */ PAD_CFG_NF(GPP_F17, UP_20K, DEEP, NF1), +/* GPP_F18 GPIO */ PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, LEVEL, INVERT), +/* GPP_F19 eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* GPP_F20 eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* GPP_F21 eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* GPP_F22 DDPF_CTRLCLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPP_F23 DDPF_CTRLDATA */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), +/* GPP_I0 DDPB_HPD0 */ PAD_CFG_NF(GPP_I0, NATIVE, DEEP, NF1), +/* GPP_I1 DDPB_HPD1 */ PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1), +/* GPP_I2 DDPB_HPD2 */ PAD_CFG_NF(GPP_I2, NATIVE, DEEP, NF1), +/* GPP_I3 DDPB_HPD3 */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* GPP_I4 EDP_HPD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* GPP_I5 DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* GPP_I6 DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* GPP_I7 DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* GPP_I8 DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* GPP_I9 DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, DN_20K, DEEP, NF1), +/* GPP_I10 DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, DN_20K, DEEP, NF1), +/* GPP_J2 n/a */ PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), +/* GPP_J3 n/a */ PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), +/* GPP_J4 CNV_BRI_DT */ PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), +/* GPP_J5 CNV_BRI_RSP */ PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), +/* GPP_J6 CNV_RGI_DT */ PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), +/* GPP_J7 CNV_RGI_RSP */ PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), +/* GPP_J8 CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), +/* GPP_J9 CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), +/* GPP_J10 n/a */ PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), +/* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} |