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Diffstat (limited to 'src/mainboard/supermicro/h8scm_fam10')
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c4
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mainboard.c2
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mptable.c2
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c2
4 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
index 6a1fd7769f..fe5fcde226 100644
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -128,7 +128,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index 90b53357ad..d0fb54145d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -97,7 +97,7 @@ static void h8scm_enable(device_t dev)
/* get_ide_dma66(); */
}
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
int add_mainboard_resources(struct lb_memory *mem)
{
return 0;
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 0c75d1a15b..2e50b84950 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin))
#else
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 70b3a0470d..6ad1484462 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();