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-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c9
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c8
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c9
3 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 461546528d..980437b201 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -226,11 +230,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index c8ed2dfda1..20522e10de 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -30,6 +30,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
@@ -171,6 +172,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -290,11 +294,15 @@ post_code(0x3D);
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 4c6292f40f..355cf820b7 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -33,6 +33,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
+#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
@@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
msr_t msr;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -210,8 +214,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
cbmem_initialize_empty();
post_code(0x41);
@@ -230,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sr5650_before_pci_init();
sb7xx_51xx_before_pci_init();
+ timestamp_add_now(TS_END_ROMSTAGE);
+
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.