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-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/Kconfig62
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/Kconfig.name2
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/Makefile.inc16
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/README22
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/board_info.txt1
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/cmos.layout102
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/devicetree.cb152
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c78
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/hda_verb.c20
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/irq_tables.c137
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h26
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/mptable.c114
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/resourcemap.c284
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c269
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/Kconfig60
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/Kconfig.name2
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/Makefile.inc16
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/board_info.txt2
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/cmos.layout102
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/devicetree.cb115
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c96
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/irq_tables.c137
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h32
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/mptable.c112
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/resourcemap.c284
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c321
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/Kconfig55
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/Kconfig.name2
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/Makefile.inc16
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl80
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl240
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl380
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl145
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl158
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/acpi_tables.c97
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/board_info.txt1
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/cmos.layout52
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/devicetree.cb123
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/dsdt.asl1766
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c55
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/irq_tables.c102
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mainboard.c80
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h39
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mptable.c128
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/resourcemap.c279
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c238
46 files changed, 0 insertions, 6600 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
deleted file mode 100644
index 928a84fc96..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_SUPERMICRO_H8DMR_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_SOCKET_F_1207
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_WINBOND_W83627HF
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select ENABLE_APIC_EXT_ID
-
-config MAINBOARD_DIR
- string
- default supermicro/h8dmr_fam10
-
-config DCACHE_RAM_BASE
- hex
- default 0xc4000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x0c000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "H8DMR-i2 (Fam10)"
-
-config MAX_CPUS
- int
- default 8
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUPERMICRO_H8DMR_FAM10
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name b/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name
deleted file mode 100644
index 379d9bb026..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8DMR_FAM10
- bool "H8DMR-i2 (Fam10)"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc b/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
deleted file mode 100644
index ffcbcc021f..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/README
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-There are a number of outstanding issues:
-
-* I'm seeing toolchain issues. I can't get this tree to compile correctly with
-gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
-CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
-disappears. This is probably not a problem related to this port specifically.
-
-* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
-shortly after the warm reset triggered by the MCP55 code. I think this too
-might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).
-
-* during startup, the CPU cores talk through each other on serial for a
-while. Again, not an issue specific to this port.
-
-* to avoid very slow LZMA decompression I use this port with LZMA compression
-disabled in CBFS. I'm not sure what's causing this particular slowness.
-
-See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
-
-Ward, 2009-09-22
diff --git a/src/mainboard/supermicro/h8dmr_fam10/board_info.txt b/src/mainboard/supermicro/h8dmr_fam10/board_info.txt
deleted file mode 100644
index 3d902b640a..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: server
diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout
deleted file mode 100644
index 331e0162bb..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout
+++ /dev/null
@@ -1,102 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-#394 7 unused
-401 1 e 1 interleave_chip_selects
-402 1 e 1 interleave_nodes
-403 1 e 1 interleave_memory_channels
-404 2 e 8 max_mem_clock
-406 1 e 2 multi_core
-412 4 e 6 debug_level
-416 5 e 10 ecc_scrub_rate
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 gart
-446 1 e 1 power_on_after_fail
-456 1 e 1 ECC_memory
-457 1 e 1 ECC_redirection
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97sms
-10 21 42ms
-10 22 84ms
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
deleted file mode 100644
index ee88c31a97..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
+++ /dev/null
@@ -1,152 +0,0 @@
-chip northbridge/amd/amdfam10/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F_1207 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x15d9 0x1511 inherit
- chip northbridge/amd/amdfam10 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # SB on link 2.0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO, game port, MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM 1-1-1
- device i2c 57 on end
- end
- end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- # chip drivers/generic/generic # PCIXA slot 1
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # PCIXB slot 2
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # PCI slot 1
- # device i2c 53 on end
- # end
- # chip drivers/generic/generic # Master MCP55 PCI-E
- # device i2c 54 on end
- # end
- # chip drivers/generic/generic # Slave MCP55 PCI-E
- # device i2c 55 on end
- # end
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on # PCI
- device pci 6.0 on end
- end
- device pci 6.1 on end # AZA
- device pci 8.0 on end # NIC
- device pci 9.0 on end # NIC
- device pci a.0 on # PCI E 5
- device pci 0.0 on end # NEC PCI-X
- device pci 0.1 on # NEC PCI-X
- device pci 4.0 on end # SCSI
- device pci 4.1 on end # SCSI
- end
- end
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- device pci 19.4 on end
- end
- end
-end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
deleted file mode 100644
index 0bb16d36b2..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-void get_bus_conf(void)
-{
-
- unsigned int apicid_base;
- struct mb_sysconf_t *m;
-
- struct device *dev;
- int i;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- get_default_pci1234(32);
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
-
- /* MCP55 */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
- if (dev) {
- m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
- }
-
- for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
- if (dev) {
- m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
- }
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- if (CONFIG(LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base+0;
-
-}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c b/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c
deleted file mode 100644
index 5d088790a5..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/hda_verb.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[0] = {};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
deleted file mode 100644
index 69327dcafa..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned int slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
-
- uint8_t sum = 0;
- int i;
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55[0];
- pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0370;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff;
- unsigned int devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8,
- 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
-#if CONFIG_CBB
- write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2,
- 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
- if (sysconf.nodes > 32) {
- write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
- 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8,
- 0, 0);
- pirq_info++;
- slot_num++;
- }
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h
deleted file mode 100644
index 1a287c6a8a..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55[8]; //1
- unsigned int apicid_mcp55;
-};
-
-#endif
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
deleted file mode 100644
index cdb2980867..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x43c6c643;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd00012d2;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0xa);
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0x16); // 22)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0x17); // 23)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0x17); // 23)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x14); // 20)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0x17); // 23)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0x15); // 21)
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 8, 0, m->apicid_mcp55, 0x16); // 22)
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 9, 0, m->apicid_mcp55, 0x15); // 21)
-
- for(j = 7; j >= 2; j--) {
- if(!m->bus_mcp55[j]) continue;
- for(i = 0; i < 4; i++) {
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
- }
-
- for(j = 0; j < 1; j++)
- for(i = 0; i < 4; i++) {
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
deleted file mode 100644
index 2398ba25d7..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
- ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
- ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
- ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
- ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
- ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
- ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp address bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// WARD CHANGED
- ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020,
- ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- // WARD CHANGED
- ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033,
- ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- // WARD CHANGED
- ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
- ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
deleted file mode 100644
index 6f6ac712c7..0000000000
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <spd.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <delay.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <southbridge/amd/common/reset.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-
-#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-
-#include "cpu/amd/quadcore/quadcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- enable_smbus();
- // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
- /* set FAN ctrl to DC mode */
- smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff);
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-}
-
-static const u8 spd_addr[] = {
- //first node
- RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-};
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = get_sysinfo();
- u32 bsp_apicid = 0, val, wants_reset;
- msr_t msr;
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
- sio_setup();
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- post_code(0x32);
-
- winbond_set_clksel_48(SUPERIO_DEV);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- update_microcode(val);
-
- post_code(0x33);
-
- cpuSetAMDMSR(0);
- post_code(0x34);
-
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
-
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
-
- wait_all_core0_started();
-#if CONFIG(LOGICAL_CPUS)
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores(bsp_apicid);
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- post_code(0x38);
-
-#if CONFIG(SET_FIDVID)
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
- msr.hi, msr.lo);
-
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
-
- post_code(0x3A);
-
- /* show final fid and vid */
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n",
- msr.hi, msr.lo);
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- wants_reset = mcp55_early_setup_x();
-
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset - shouldn't see this message!!!\n");
- }
-
- if (wants_reset)
- printk(BIOS_DEBUG, "mcp55_early_setup_x wants additional reset!\n");
-
- post_code(0x3B);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- post_code(0x3D);
-
- // printk(BIOS_DEBUG, "enable_smbus()\n");
- // enable_smbus(); /* enable in sio_setup */
-
- post_code(0x40);
-
- raminit_amdmct(sysinfo);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- amdmct_cbmem_store_info(sysinfo);
-
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] node = The node on which this chain is located
- * @param[in] link = The link on the host for this chain
- * @param[out] List = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
- }
-
- return 0;
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig
deleted file mode 100644
index 55d1153c7b..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_SUPERMICRO_H8QME_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_SOCKET_F_1207
- select DIMM_DDR2
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_AMD_AMD8132
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_WINBOND_W83627HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select ENABLE_APIC_EXT_ID
-
-config MAINBOARD_DIR
- string
- default supermicro/h8qme_fam10
-
-config DCACHE_RAM_BASE
- hex
- default 0xc4000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x0c000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "H8QME-2+ (Fam10)"
-
-config MAX_CPUS
- int
- default 16
-
-config MAX_PHYSICAL_CPUS
- int
- default 4
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_SUPERMICRO_H8QME_FAM10
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name b/src/mainboard/supermicro/h8qme_fam10/Kconfig.name
deleted file mode 100644
index d7f1933d60..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8QME_FAM10
- bool "H8QME-2+ (Fam10)"
diff --git a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc b/src/mainboard/supermicro/h8qme_fam10/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/supermicro/h8qme_fam10/board_info.txt b/src/mainboard/supermicro/h8qme_fam10/board_info.txt
deleted file mode 100644
index cb3000fd04..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm
diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout
deleted file mode 100644
index 331e0162bb..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout
+++ /dev/null
@@ -1,102 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-#394 7 unused
-401 1 e 1 interleave_chip_selects
-402 1 e 1 interleave_nodes
-403 1 e 1 interleave_memory_channels
-404 2 e 8 max_mem_clock
-406 1 e 2 multi_core
-412 4 e 6 debug_level
-416 5 e 10 ecc_scrub_rate
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 gart
-446 1 e 1 power_on_after_fail
-456 1 e 1 ECC_memory
-457 1 e 1 ECC_redirection
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97sms
-10 21 42ms
-10 22 84ms
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
deleted file mode 100644
index 317d643d9a..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ /dev/null
@@ -1,115 +0,0 @@
-chip northbridge/amd/amdfam10/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F_1207 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x15d9 0x1511 inherit
- chip northbridge/amd/amdfam10 # Northbridge / RAM controller
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # SB on link 2
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO, game port, MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end
- device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
- chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.1 off end # AZA
- device pci 7.0 on
- device pci 1.0 on end
- end
- device pci 8.0 off end
- device pci 9.0 off end
- device pci a.0 on end # PCI E 5
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
- device pci e.0 on end # PCI E 1
- device pci f.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.0 on
- chip southbridge/amd/amd8132
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on
- device pci 3.0 on end
- device pci 3.1 on end
- end
- device pci 1.1 on end
- end
- end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- device pci 19.4 on end
- end
- end
-end
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
deleted file mode 100644
index 56ea43c7fe..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned int sbdn3;
-
-void get_bus_conf(void)
-{
-
- unsigned int apicid_base;
- struct mb_sysconf_t *m;
-
- struct device *dev;
- int i;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- get_default_pci1234(32);
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
-
- m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
- sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
- /* MCP55 */
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
-
- if (dev) {
- m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
- }
-
- for(i = 2; i < 8; i++) {
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
- if (dev) {
- m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
- }
- }
-
- /* 8132_1 */
-
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0));
- m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_8132_2++;
-
- /* 8132_2 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
- m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-/*I/O APICs: APIC ID Version State Address*/
- if (CONFIG(LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- m->apicid_mcp55 = apicid_base+0;
- m->apicid_8132_1 = apicid_base+1;
- m->apicid_8132_2 = apicid_base+2;
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
deleted file mode 100644
index b77e86209b..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned int slot_num;
- uint8_t *v;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
-
- uint8_t sum = 0;
- int i;
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_mcp55[0];
- pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x0364;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-//pci bridge
- write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
- 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
- pirq_info++;
- slot_num++;
-
- for (i = 1; i < sysconf.hc_possible_num; i++) {
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
- unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff;
- unsigned int devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0,
- 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
- pirq_info++;
- slot_num++;
- }
-
-#if CONFIG_CBB
- write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2,
- 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
- pirq_info++;
- slot_num++;
- if (sysconf.nodes > 32) {
- write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
- 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0,
- 0, 0);
- pirq_info++;
- slot_num++;
- }
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
deleted file mode 100644
index f93f9e8380..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_mcp55[8]; //1
- unsigned int apicid_mcp55;
-
- unsigned char bus_8132_0; //7
- unsigned char bus_8132_1; //8
- unsigned char bus_8132_2; //9
- unsigned int apicid_8132_1;
- unsigned int apicid_8132_2;
-};
-
-#endif
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
deleted file mode 100644
index 7e6237f1f6..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-extern unsigned int sbdn3;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct mb_sysconf_t *m;
- unsigned int sbdn;
- int i, j, bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
- }
-
- dword = 0x00000ab5;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x5ab0a500;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0xa000000b;
- pci_write_config32(dev, 0x84, dword);
-
- }
-
-
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
-
- smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
- smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
-
- for(j = 7;j >= 2; j--) {
- if(!m->bus_mcp55[j]) continue;
- for(i = 0; i < 4; i++) {
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
- }
- }
-
- for(j = 0; j < 1; j++)
- for(i = 0; i < 4; i++) {
- smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
- }
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
deleted file mode 100644
index 2398ba25d7..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- // ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
- ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
- ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
- ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
- ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
- ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
- ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- // ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
- ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp address bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// WARD CHANGED
- ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020,
- ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
- ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- // WARD CHANGED
- ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033,
- ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- // WARD CHANGED
- ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
- ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
deleted file mode 100644
index 7c489ca8dd..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <spd.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <delay.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <southbridge/amd/common/reset.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-
-#include "cpu/amd/quadcore/quadcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
- smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
- smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
-}
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
- enable_smbus();
-// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
- smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
- dword |= (1 << 0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
- dword |= (1 << 16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
-}
-
-static const u8 spd_addr[] = {
- /* first node */
- RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- /* second node */
- RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-#if CONFIG_MAX_PHYSICAL_CPUS > 2
- /* third node */
- RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
- /* fourth node */
- RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-};
-
-#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
-#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
-#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
-
-static void write_GPIO(void)
-{
- pnp_enter_conf_state(GPIO1_DEV);
- pnp_set_logical_device(GPIO1_DEV);
- pnp_write_config(GPIO1_DEV, 0x30, 0x01);
- pnp_write_config(GPIO1_DEV, 0x60, 0x00);
- pnp_write_config(GPIO1_DEV, 0x61, 0x00);
- pnp_write_config(GPIO1_DEV, 0x62, 0x00);
- pnp_write_config(GPIO1_DEV, 0x63, 0x00);
- pnp_write_config(GPIO1_DEV, 0x70, 0x00);
- pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
- pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
- pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
- pnp_exit_conf_state(GPIO1_DEV);
-
- pnp_enter_conf_state(GPIO2_DEV);
- pnp_set_logical_device(GPIO2_DEV);
- pnp_write_config(GPIO2_DEV, 0x30, 0x01);
- pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
- pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
- pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
- pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
- pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
- pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
- pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
- pnp_exit_conf_state(GPIO2_DEV);
-
- pnp_enter_conf_state(GPIO3_DEV);
- pnp_set_logical_device(GPIO3_DEV);
- pnp_write_config(GPIO3_DEV, 0x30, 0x00);
- pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
- pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
- pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
- pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
- pnp_exit_conf_state(GPIO3_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = get_sysinfo();
- u32 bsp_apicid = 0, val, wants_reset;
- msr_t msr;
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
- sio_setup();
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- post_code(0x32);
-
- winbond_set_clksel_48(SUPERIO_DEV);
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
- write_GPIO();
- printk(BIOS_DEBUG, "\n");
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- update_microcode(val);
-
- post_code(0x33);
-
- cpuSetAMDMSR(0);
- post_code(0x34);
-
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
-
- wait_all_core0_started();
-#if CONFIG(LOGICAL_CPUS)
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores(bsp_apicid);
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- post_code(0x38);
-
-#if CONFIG(SET_FIDVID)
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
-
- post_code(0x3A);
-
- /* show final fid and vid */
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
-
- init_timer(); // Need to use TMICT to synchronize FID/VID
-
- wants_reset = mcp55_early_setup_x();
-
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset - shouldn't see this message!!!\n");
- }
-
- if (wants_reset)
- printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
-
- post_code(0x3B);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- post_code(0x3D);
-
-// printk(BIOS_DEBUG, "enable_smbus()\n");
-// enable_smbus(); /* enable in sio_setup */
-
- post_code(0x40);
-
- raminit_amdmct(sysinfo);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- amdmct_cbmem_store_info(sysinfo);
-
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] node = The node on which this chain is located
- * @param[in] link = The link on the host for this chain
- * @param[out] List = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
- }
-
- return 0;
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
deleted file mode 100644
index 2e6db0e1ed..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-if BOARD_SUPERMICRO_H8SCM_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_SOCKET_C32_NON_AGESA
- select DIMM_DDR3
- select DIMM_REGISTERED
- select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_AMD_SR5650
- select SOUTHBRIDGE_AMD_SB700
- select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
- select SUPERIO_WINBOND_W83627HF
- select SUPERIO_NUVOTON_WPCM450
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_2048
- select ENABLE_APIC_EXT_ID
-
-config MAINBOARD_DIR
- string
- default supermicro/h8scm_fam10
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "H8SCM (Fam10)"
-
-config MAX_CPUS
- int
- default 16
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_AMD_H8SCM_FAM10
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig.name b/src/mainboard/supermicro/h8scm_fam10/Kconfig.name
deleted file mode 100644
index 03ff6bc5fc..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8SCM_FAM10
- bool "H8SCM (Fam10)"
diff --git a/src/mainboard/supermicro/h8scm_fam10/Makefile.inc b/src/mainboard/supermicro/h8scm_fam10/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl
deleted file mode 100644
index acaa5bae32..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi/cpstate.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system. It is included into the DSDT for each
- * core. It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
- {
- Scope (\_PR) {
- Device (CPU0) {
- Name (_HID, "ACPI0007")
- Name (_UID, 0)
- #include "cpstate.asl"
- }
- Device (CPU1) {
- Name (_HID, "ACPI0007")
- Name (_UID, 1)
- #include "cpstate.asl"
- }
- Device (CPU2) {
- Name (_HID, "ACPI0007")
- Name (_UID, 2)
- #include "cpstate.asl"
- }
- Device (CPU3) {
- Name (_HID, "ACPI0007")
- Name (_UID, 3)
- #include "cpstate.asl"
- }
- }
-*/
- /* P-state support: The maximum number of P-states supported by the */
- /* CPUs we'll use is 6. */
- /* Get from AMI BIOS. */
- Name(_PSS, Package(){
- Package ()
- {
- 0x00000AF0,
- 0x0000BF81,
- 0x00000002,
- 0x00000002,
- 0x00000000,
- 0x00000000
- },
-
- Package ()
- {
- 0x00000578,
- 0x000076F2,
- 0x00000002,
- 0x00000002,
- 0x00000001,
- 0x00000001
- }
- })
-
- Name(_PCT, Package(){
- ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
- ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
- })
-
- Method(_PPC, 0){
- Return(0)
- }
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl
deleted file mode 100644
index 5c155cf301..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "ide.asl"
- }
- }
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
- 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
- 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
- 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
- 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
- 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
- Field(ICRG, AnyAcc, NoLock, Preserve)
-{
- PPTS, 8, /* Primary PIO Slave Timing */
- PPTM, 8, /* Primary PIO Master Timing */
- OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
- PMTM, 8, /* Primary MWDMA Master Timing */
- OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
- OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
- PPSM, 4, /* Primary PIO slave Mode */
- OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
- OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
- PDSM, 4, /* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
- Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
- Increment(Local0)
- Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
- Increment(Local1)
- Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
- Name (_ADR, Zero)
- Method(_GTM, 0)
- {
- NAME(OTBF, Buffer(20) { /* out buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
- CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
- /* Just return if the channel is disabled */
- If(And(PPCR, 0x01)) { /* primary PIO control */
- Return(OTBF)
- }
-
- /* Always tell them independent timing available and IOChannelReady used on both drives */
- Or(BFFG, 0x1A, BFFG)
-
- Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
- Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
-
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */
- Or(BFFG, 0x01, BFFG)
- Store(DerefOf(Index(UDTT, PDMM)), DSD0)
- }
- Else {
- Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
- }
-
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */
- Or(BFFG, 0x04, BFFG)
- Store(DerefOf(Index(UDTT, PDSM)), DSD1)
- }
- Else {
- Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
- }
-
- Return(OTBF) /* out buffer */
- } /* End Method(_GTM) */
-
- Method(_STM, 3, NotSerialized)
- {
- NAME(INBF, Buffer(20) { /* in buffer */
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
- })
-
- CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
- CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
- CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
- CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
- CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
- Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
- Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
- Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
- Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
- Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
- Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDMM,)
- Or(PDCR, 0x01, PDCR)
- }
- Else {
- If(LNotEqual(DSD0, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTM)
- }
- }
-
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
- Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Divide(Local0, 7, PDSM,)
- Or(PDCR, 0x02, PDCR)
- }
- Else {
- If(LNotEqual(DSD1, 0xFFFFFFFF)) {
- Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
- Store(DerefOf(Index(MDRT, Local0)), PMTS)
- }
- }
- /* Return(INBF) */
- } /*End Method(_STM) */
- Device(MST)
- {
- Name(_ADR, 0)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xA0, CMDA)
- Store(0xA0, CMDB)
- Store(0xA0, CMDC)
-
- Or(PPMM, 0x08, POMD)
-
- If(And(PDCR, 0x01)) {
- Or(PDMM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTM),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(MST) */
-
- Device(SLAV)
- {
- Name(_ADR, 1)
- Method(_GTF) {
- Name(CMBF, Buffer(21) {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
- })
- CreateByteField(CMBF, 1, POMD)
- CreateByteField(CMBF, 8, DMMD)
- CreateByteField(CMBF, 5, CMDA)
- CreateByteField(CMBF, 12, CMDB)
- CreateByteField(CMBF, 19, CMDC)
-
- Store(0xB0, CMDA)
- Store(0xB0, CMDB)
- Store(0xB0, CMDC)
-
- Or(PPSM, 0x08, POMD)
-
- If(And(PDCR, 0x02)) {
- Or(PDSM, 0x40, DMMD)
- }
- Else {
- Store(Match
- (MDTT, MLE, GTTM(PMTS),
- MTR, 0, 0), Local0)
- If(LLess(Local0, 3)) {
- Or(0x20, Local0, DMMD)
- }
- }
- Return(CMBF)
- }
- } /* End Device(SLAV) */
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl
deleted file mode 100644
index a8c47fdb7c..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- Package (0x04) { 0xFFFF, Zero, INTA, Zero },
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, INTD, 0 },
- Package(){0x0003FFFF, 1, INTA, 0 },
- Package(){0x0003FFFF, 2, INTB, 0 },
- Package(){0x0003FFFF, 3, INTC, 0 },
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, INTB, 0 },
- Package(){0x0005FFFF, 1, INTC, 0 },
- Package(){0x0005FFFF, 2, INTD, 0 },
- Package(){0x0005FFFF, 3, INTA, 0 },
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* Bus 0, Dev 9 - PCIe Bridge for network card */
- Package(){0x0009FFFF, 0, INTB, 0 },
- Package(){0x0009FFFF, 1, INTC, 0 },
- Package(){0x0009FFFF, 2, INTD, 0 },
- Package(){0x0009FFFF, 3, INTA, 0 },
-
- /* Bus 0, Dev a - PCIe Bridge for network card */
- Package(){0x000AFFFF, 0, INTC, 0 },
- Package(){0x000AFFFF, 1, INTD, 0 },
- Package(){0x000AFFFF, 2, INTA, 0 },
- Package(){0x000AFFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev b - */
- Package(){0x000BFFFF, 0, INTD, 0 },
- Package(){0x000BFFFF, 1, INTA, 0 },
- Package(){0x000BFFFF, 2, INTB, 0 },
- Package(){0x000BFFFF, 3, INTC, 0 },
-
- /* Bus 0, Dev c - */
- Package(){0x000CFFFF, 0, INTA, 0 },
- Package(){0x000CFFFF, 1, INTB, 0 },
- Package(){0x000CFFFF, 2, INTC, 0 },
- Package(){0x000CFFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 17 - SATA controller */
- Package(){0x0011FFFF, 0, INTG, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0012FFFF, 0, INTA, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
- Package(){0x0012FFFF, 2, INTC, 0 },
- Package(){0x0012FFFF, 3, INTD, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTD, 0 },
- Package(){0x0013FFFF, 2, INTA, 0 },
- Package(){0x0013FFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- Package (0x04) { 0xFFFF, Zero, Zero, 16 },
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- Package(){0x0002FFFF, 1, 0, 19 },
- Package(){0x0002FFFF, 2, 0, 16 },
- Package(){0x0002FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
- Package(){0x0003FFFF, 1, 0, 16 },
- Package(){0x0003FFFF, 2, 0, 17 },
- Package(){0x0003FFFF, 3, 0, 18 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- Package(){0x0004FFFF, 1, 0, 17 },
- Package(){0x0004FFFF, 2, 0, 18 },
- Package(){0x0004FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- Package(){0x0005FFFF, 1, 0, 18 },
- Package(){0x0005FFFF, 2, 0, 19 },
- Package(){0x0005FFFF, 3, 0, 16 },
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- Package(){0x0006FFFF, 1, 0, 19 },
- Package(){0x0006FFFF, 2, 0, 16 },
- Package(){0x0006FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- Package(){0x0007FFFF, 1, 0, 16 },
- Package(){0x0007FFFF, 2, 0, 17 },
- Package(){0x0007FFFF, 3, 0, 18 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* Bus 0, Dev 9 - PCIe Bridge for network card */
- Package(){0x0009FFFF, 0, 0, 17 },
- Package(){0x0009FFFF, 1, 0, 18 },
- Package(){0x0009FFFF, 2, 0, 19 },
- Package(){0x0009FFFF, 3, 0, 16 },
-
- /* Bus 0, Dev A - PCIe Bridge for network card */
- Package(){0x000AFFFF, 0, 0, 18 },
- Package(){0x000AFFFF, 1, 0, 19 },
- Package(){0x000AFFFF, 2, 0, 16 },
- Package(){0x000AFFFF, 3, 0, 17 },
-
- /* Bus 0, Dev b - */
- Package(){0x000BFFFF, 0, 0, 19 },
- Package(){0x000BFFFF, 1, 0, 16 },
- Package(){0x000BFFFF, 2, 0, 17 },
- Package(){0x000BFFFF, 3, 0, 18 },
-
- /* Bus 0, Dev c - */
- Package(){0x000CFFFF, 0, 0, 16 },
- Package(){0x000CFFFF, 1, 0, 17 },
- Package(){0x000CFFFF, 2, 0, 18 },
- Package(){0x000CFFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 17 - SATA controller */
- Package(){0x0011FFFF, 0, 0, 22 },
-
- /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
- Package(){0x0012FFFF, 0, 0, 16 },
- Package(){0x0012FFFF, 1, 0, 17 },
- Package(){0x0012FFFF, 2, 0, 18 },
- Package(){0x0012FFFF, 3, 0, 19 },
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 19 },
- Package(){0x0013FFFF, 2, 0, 16 },
- Package(){0x0013FFFF, 3, 0, 17 },
- /* Package(){0x00130004, 2, 0, 18 }, */
- /* Package(){0x00130005, 3, 0, 19 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
-
- Name(APR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
-
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 45 },
- Package(){0x0000FFFF, 1, 0, 46 },
- Package(){0x0000FFFF, 2, 0, 47 },
- Package(){0x0000FFFF, 3, 0, 44 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 46 },
- Package(){0x0000FFFF, 1, 0, 47 },
- Package(){0x0000FFFF, 2, 0, 44 },
- Package(){0x0000FFFF, 3, 0, 45 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 47 },
- Package(){0x0000FFFF, 1, 0, 44 },
- Package(){0x0000FFFF, 2, 0, 45 },
- Package(){0x0000FFFF, 3, 0, 46 },
- })
-
- Name(PS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
-
- Name(APS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
- Name(PSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
-
- Name(APSa, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PSb, Package(){
- /* PCIe slot - Hooked to PCIe slot 11 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APSb, Package(){
- /* PCIe slot - Hooked to PCIe slot 11 */
- Package(){0x0000FFFF, 0, 0, 32 },
- Package(){0x0000FFFF, 1, 0, 33 },
- Package(){0x0000FFFF, 2, 0, 34 },
- Package(){0x0000FFFF, 3, 0, 34 },
- })
-
- Name(PSc, Package(){
- /* PCIe slot - Hooked to PCIe slot 12 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
-
- Name(APSc, Package(){
- /* PCIe slot - Hooked to PCIe slot 12 */
- Package(){0x0000FFFF, 0, 0, 36 },
- Package(){0x0000FFFF, 1, 0, 37 },
- Package(){0x0000FFFF, 2, 0, 38 },
- Package(){0x0000FFFF, 3, 0, 39 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl
deleted file mode 100644
index cb9b221ba3..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00110000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P0IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P1IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (LGreater(P2IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (LGreater(P3IS,0)) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
- }
-
- if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
- }
-
- if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
- }
-
- if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
- }
- }
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl
deleted file mode 100644
index a3ccb97ff9..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-Method(UCOC, 0) {
- Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
- Scope (\_GPE) {
- Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
- }
- }
- }
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
deleted file mode 100644
index e9f181b836..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include "mb_sysconf.h"
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- u32 dword;
- u32 gsi_base = 0;
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB700 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
- IO_APIC_ADDR, gsi_base);
- /* IOAPIC on rs5690 */
- gsi_base += 24; /* SB700 has 24 IOAPIC entries. */
- dev = pcidev_on_root(0, 0);
- if (dev) {
- pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1,
- dword, gsi_base);
- }
-
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
-
-unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
-{
- uint8_t *p;
-
- uint32_t apicid_sp5100;
- uint32_t apicid_sr5650;
-
- apicid_sp5100 = 0x20;
- apicid_sr5650 = apicid_sp5100 + 1;
-
- /* Describe NB IOAPIC */
- p = (uint8_t *)current;
- p[0] = 0x48; /* Entry type */
- p[1] = 0; /* Device */
- p[2] = 0; /* Bus */
- p[3] = 0x0; /* Data */
- p[4] = apicid_sr5650; /* IOAPIC ID */
- p[5] = 0x1; /* Device 0 Function 1 */
- p[6] = 0x0; /* Northbridge bus */
- p[7] = 0x1; /* Variety */
- current += 8;
-
- /* Describe SB IOAPIC */
- p = (uint8_t *)current;
- p[0] = 0x48; /* Entry type */
- p[1] = 0; /* Device */
- p[2] = 0; /* Bus */
- p[3] = 0xd7; /* Data */
- p[4] = apicid_sp5100; /* IOAPIC ID */
- p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
- p[6] = 0x0; /* Southbridge bus */
- p[7] = 0x1; /* Variety */
- current += 8;
-
- return current;
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/board_info.txt b/src/mainboard/supermicro/h8scm_fam10/board_info.txt
deleted file mode 100644
index 3d902b640a..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: server
diff --git a/src/mainboard/supermicro/h8scm_fam10/cmos.layout b/src/mainboard/supermicro/h8scm_fam10/cmos.layout
deleted file mode 100644
index 6c3d3f6c9e..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 gart
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
deleted file mode 100644
index 2799a26751..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
+++ /dev/null
@@ -1,123 +0,0 @@
-# GPP1 (dev2,3) --> slot 7
-# GPP2 (dev12) --> slot 6
-# GPP3A (dev9,A) --> Lan1, Lan2
-
-# sample config for supermicro/h8scm_fam10
-chip northbridge/amd/amdfam10/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_C32 #L1 and DDR3
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x15d9 0x1511 inherit
- chip northbridge/amd/amdfam10
- ##device pci 18.0 on end
- ##device pci 18.0 on end
- device pci 18.0 on # northbridge
- chip southbridge/amd/sr5650
- device pci 0.0 on end # HT 0x9600
- device pci 0.1 on end # CLKCONFIG
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
- device pci 3.0 off end # PCIE P2P bridge 0x960b
- device pci 4.0 off end # PCIE P2P bridge 0x9604
- device pci 5.0 off end # PCIE P2P bridge 0x9605
- device pci 6.0 on end # PCIE P2P bridge 0x9606
- device pci 7.0 on end # PCIE P2P bridge 0x9607
- device pci 8.0 on end # NB/SB Link P2P bridge
- device pci 9.0 on end #
- device pci a.0 on end #
- device pci b.0 on end #
- device pci c.0 on end #
- device pci d.0 on end #
- register "gpp1_configuration" = "0" # Configuration 16:0 default
- register "gpp2_configuration" = "1" # Configuration 8:8
- #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
- register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
- register "port_enable" = "0x1ffc"
- end
- chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.1 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.1 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on end # SM
- device pci 14.1 on end # IDE 0x439c
- device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec.
- device pci 14.3 on # LPC 0x439d
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 off # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # SFI
- io 0x62 = 0x100
- end
- device pnp 2e.7 off # GPIO_GAME_MIDI
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # WDTO_PLED
- device pnp 2e.9 off end # GPIO_SUSLED
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end #superio/winbond/w83627hf
- end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/sb700
- end # device pci 18.0
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- device pci 19.4 on end
- end
- end #domain
- #for node 32 to node 63
-# device domain 0 on
-# chip northbridge/amd/amdfam10
-# device pci 00.0 on end# northbridge
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.1 on end
-# device pci 00.2 on end
-# device pci 00.3 on end
-# device pci 00.4 on end
-# device pci 00.5 on end
-# end
-# end #domain
-
-end
diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl
deleted file mode 100644
index 4dfa9995b9..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl
+++ /dev/null
@@ -1,1766 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Data to be patched by the BIOS during POST */
- /* FIXME the patching is not done yet! */
- /* Memory related values */
- Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
-
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
- /* USB overcurrent mapping pins. */
- Name(UOM0, 0)
- Name(UOM1, 2)
- Name(UOM2, 0)
- Name(UOM3, 7)
- Name(UOM4, 2)
- Name(UOM5, 2)
- Name(UOM6, 6)
- Name(UOM7, 2)
- Name(UOM8, 6)
- Name(UOM9, 6)
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PMOD, One) /* Assume APIC */
-
- /*
- * Processor Object
- *
- */
- Scope (\_PR) { /* define processor scope */
- Device (CPU0) {
- Name (_HID, "ACPI0007")
- Name (_UID, 0)
- #include "acpi/cpstate.asl"
- }
- Device (CPU1) {
- Name (_HID, "ACPI0007")
- Name (_UID, 1)
- #include "acpi/cpstate.asl"
- }
- Device (CPU2) {
- Name (_HID, "ACPI0007")
- Name (_UID, 2)
- #include "acpi/cpstate.asl"
- }
- Device (CPU3) {
- Name (_HID, "ACPI0007")
- Name (_UID, 3)
- #include "acpi/cpstate.asl"
- }
- Device (CPU4) {
- Name (_HID, "ACPI0007")
- Name (_UID, 4)
- #include "acpi/cpstate.asl"
- }
- Device (CPU5) {
- Name (_HID, "ACPI0007")
- Name (_UID, 5)
- #include "acpi/cpstate.asl"
- }
- } /* End _PR scope */
-
- /* PIC IRQ mapping registers, C00h-C01h */
- OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
- Field(PRQM, ByteAcc, NoLock, Preserve) {
- PRQI, 0x00000008,
- PRQD, 0x00000008, /* Offset: 1h */
- }
- IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
- PINA, 0x00000008, /* Index 0 */
- PINB, 0x00000008, /* Index 1 */
- PINC, 0x00000008, /* Index 2 */
- PIND, 0x00000008, /* Index 3 */
- AINT, 0x00000008, /* Index 4 */
- SINT, 0x00000008, /* Index 5 */
- , 0x00000008, /* Index 6 */
- AAUD, 0x00000008, /* Index 7 */
- AMOD, 0x00000008, /* Index 8 */
- PINE, 0x00000008, /* Index 9 */
- PINF, 0x00000008, /* Index A */
- PING, 0x00000008, /* Index B */
- PINH, 0x00000008, /* Index C */
- }
-
- /* PCI Error control register */
- OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
- Field(PERC, ByteAcc, NoLock, Preserve) {
- SENS, 0x00000001,
- PENS, 0x00000001,
- SENE, 0x00000001,
- PENE, 0x00000001,
- }
-
- /* Client Management index/data registers */
- OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
- Field(CMT, ByteAcc, NoLock, Preserve) {
- CMTI, 8,
- /* Client Management Data register */
- G64E, 1,
- G64O, 1,
- G32O, 2,
- , 2,
- GPSL, 2,
- }
-
- /* GPM Port register */
- OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
- Field(GPT, ByteAcc, NoLock, Preserve) {
- GPB0,1,
- GPB1,1,
- GPB2,1,
- GPB3,1,
- GPB4,1,
- GPB5,1,
- GPB6,1,
- GPB7,1,
- }
-
- /* Flash ROM program enable register */
- OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
- Field(FRE, ByteAcc, NoLock, Preserve) {
- , 0x00000006,
- FLRE, 0x00000001,
- }
-
- /* PM2 index/data registers */
- OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
- Field(PM2R, ByteAcc, NoLock, Preserve) {
- PM2I, 0x00000008,
- PM2D, 0x00000008,
- }
-
- /* Power Management I/O registers */
- OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
- Field(PIOR, ByteAcc, NoLock, Preserve) {
- PIOI, 0x00000008,
- PIOD, 0x00000008,
- }
- IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
- Offset(0x00), /* MiscControl */
- , 1,
- T1EE, 1,
- T2EE, 1,
- Offset(0x01), /* MiscStatus */
- , 1,
- T1E, 1,
- T2E, 1,
- Offset(0x04), /* SmiWakeUpEventEnable3 */
- , 7,
- SSEN, 1,
- Offset(0x07), /* SmiWakeUpEventStatus3 */
- , 7,
- CSSM, 1,
- Offset(0x10), /* AcpiEnable */
- , 6,
- PWDE, 1,
- Offset(0x1C), /* ProgramIoEnable */
- , 3,
- MKME, 1,
- IO3E, 1,
- IO2E, 1,
- IO1E, 1,
- IO0E, 1,
- Offset(0x1D), /* IOMonitorStatus */
- , 3,
- MKMS, 1,
- IO3S, 1,
- IO2S, 1,
- IO1S, 1,
- IO0S,1,
- Offset(0x20), /* AcpiPmEvtBlk */
- APEB, 16,
- Offset(0x36), /* GEvtLevelConfig */
- , 6,
- ELC6, 1,
- ELC7, 1,
- Offset(0x37), /* GPMLevelConfig0 */
- , 3,
- PLC0, 1,
- PLC1, 1,
- PLC2, 1,
- PLC3, 1,
- PLC8, 1,
- Offset(0x38), /* GPMLevelConfig1 */
- , 1,
- PLC4, 1,
- PLC5, 1,
- , 1,
- PLC6, 1,
- PLC7, 1,
- Offset(0x3B), /* PMEStatus1 */
- GP0S, 1,
- GM4S, 1,
- GM5S, 1,
- APS, 1,
- GM6S, 1,
- GM7S, 1,
- GP2S, 1,
- STSS, 1,
- Offset(0x55), /* SoftPciRst */
- SPRE, 1,
- , 1,
- , 1,
- PNAT, 1,
- PWMK, 1,
- PWNS, 1,
-
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
-
- Offset(0x65), /* UsbPMControl */
- , 4,
- URRE, 1,
- Offset(0x68), /* MiscEnable68 */
- , 3,
- TMTE, 1,
- , 1,
- Offset(0x92), /* GEVENTIN */
- , 7,
- E7IS, 1,
- Offset(0x96), /* GPM98IN */
- G8IS, 1,
- G9IS, 1,
- Offset(0x9A), /* EnhanceControl */
- ,7,
- HPDE, 1,
- Offset(0xA8), /* PIO7654Enable */
- IO4E, 1,
- IO5E, 1,
- IO6E, 1,
- IO7E, 1,
- Offset(0xA9), /* PIO7654Status */
- IO4S, 1,
- IO5S, 1,
- IO6S, 1,
- IO7S, 1,
- }
-
- /* PM1 Event Block
- * First word is PM1_Status, Second word is PM1_Enable
- */
- OperationRegion(P1EB, SystemIO, APEB, 0x04)
- Field(P1EB, ByteAcc, NoLock, Preserve) {
- TMST, 1,
- , 3,
- BMST, 1,
- GBST, 1,
- Offset(0x01),
- PBST, 1,
- , 1,
- RTST, 1,
- , 3,
- PWST, 1,
- SPWS, 1,
- Offset(0x02),
- TMEN, 1,
- , 4,
- GBEN, 1,
- Offset(0x03),
- PBEN, 1,
- , 1,
- RTEN, 1,
- , 3,
- PWDA, 1,
- }
-
- Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
- /* Byte offsets are computed using the following technique:
- * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
- * The 8 comes from 8 functions per device, and 4096 bytes per function config space
- */
- Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
- STB5, 32,
- Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
- PT0D, 1,
- PT1D, 1,
- PT2D, 1,
- PT3D, 1,
- PT4D, 1,
- PT5D, 1,
- PT6D, 1,
- PT7D, 1,
- PT8D, 1,
- PT9D, 1,
- Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
- SBIE, 1,
- SBME, 1,
- Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
- SBRI, 8,
- Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
- SBB1, 32,
- Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
- ,14,
- P92E, 1, /* Port92 decode enable */
- }
-
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
- Field(SB5, AnyAcc, NoLock, Preserve){
- /* Port 0 */
- Offset(0x120), /* Port 0 Task file status */
- P0ER, 1,
- , 2,
- P0DQ, 1,
- , 3,
- P0BY, 1,
- Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
- , 4,
- P0IS, 4,
- Offset(0x12C), /* Port 0 Serial ATA control */
- P0DI, 4,
- Offset(0x130), /* Port 0 Serial ATA error */
- , 16,
- P0PR, 1,
-
- /* Port 1 */
- offset(0x1A0), /* Port 1 Task file status */
- P1ER, 1,
- , 2,
- P1DQ, 1,
- , 3,
- P1BY, 1,
- Offset(0x1A8), /* Port 1 Serial ATA status */
- P1DD, 4,
- , 4,
- P1IS, 4,
- Offset(0x1AC), /* Port 1 Serial ATA control */
- P1DI, 4,
- Offset(0x1B0), /* Port 1 Serial ATA error */
- , 16,
- P1PR, 1,
-
- /* Port 2 */
- Offset(0x220), /* Port 2 Task file status */
- P2ER, 1,
- , 2,
- P2DQ, 1,
- , 3,
- P2BY, 1,
- Offset(0x228), /* Port 2 Serial ATA status */
- P2DD, 4,
- , 4,
- P2IS, 4,
- Offset(0x22C), /* Port 2 Serial ATA control */
- P2DI, 4,
- Offset(0x230), /* Port 2 Serial ATA error */
- , 16,
- P2PR, 1,
-
- /* Port 3 */
- Offset(0x2A0), /* Port 3 Task file status */
- P3ER, 1,
- , 2,
- P3DQ, 1,
- , 3,
- P3BY, 1,
- Offset(0x2A8), /* Port 3 Serial ATA status */
- P3DD, 4,
- , 4,
- P3IS, 4,
- Offset(0x2AC), /* Port 3 Serial ATA control */
- P3DI, 4,
- Offset(0x2B0), /* Port 3 Serial ATA error */
- , 16,
- P3PR, 1,
- }
- }
-
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
-
- Method(OSFL, 0){
-
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if(CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
- }
-
- Method(_PIC, 0x01, NotSerialized)
- {
- If (Arg0)
- {
- \_SB.CIRQ()
- }
- Store(Arg0, PMOD)
- }
- Method(CIRQ, 0x00, NotSerialized){
- Store(0, PINA)
- Store(0, PINB)
- Store(0, PINC)
- Store(0, PIND)
- Store(0, PINE)
- Store(0, PINF)
- Store(0, PING)
- Store(0, PINH)
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
- })
-
- Name(PITF, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){9}
- })
-
- Device(INTA) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 1)
-
- Method(_STA, 0) {
- if (PINA) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTA._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKA\\_DIS\n") */
- Store(0, PINA)
- } /* End Method(_SB.INTA._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTA._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINA, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTA._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKA\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINA)
- } /* End Method(_SB.INTA._SRS) */
- } /* End Device(INTA) */
-
- Device(INTB) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 2)
-
- Method(_STA, 0) {
- if (PINB) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTB._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKB\\_DIS\n") */
- Store(0, PINB)
- } /* End Method(_SB.INTB._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTB._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINB, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTB._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKB\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINB)
- } /* End Method(_SB.INTB._SRS) */
- } /* End Device(INTB) */
-
- Device(INTC) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 3)
-
- Method(_STA, 0) {
- if (PINC) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTC._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKC\\_DIS\n") */
- Store(0, PINC)
- } /* End Method(_SB.INTC._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTC._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINC, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTC._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKC\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINC)
- } /* End Method(_SB.INTC._SRS) */
- } /* End Device(INTC) */
-
- Device(INTD) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
-
- Method(_STA, 0) {
- if (PIND) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTD._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKD\\_DIS\n") */
- Store(0, PIND)
- } /* End Method(_SB.INTD._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTD._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PIND, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTD._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKD\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PIND)
- } /* End Method(_SB.INTD._SRS) */
- } /* End Device(INTD) */
-
- Device(INTE) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 5)
-
- Method(_STA, 0) {
- if (PINE) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTE._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKE\\_DIS\n") */
- Store(0, PINE)
- } /* End Method(_SB.INTE._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTE._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINE, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTE._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKE\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINE)
- } /* End Method(_SB.INTE._SRS) */
- } /* End Device(INTE) */
-
- Device(INTF) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 6)
-
- Method(_STA, 0) {
- if (PINF) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTF._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKF\\_DIS\n") */
- Store(0, PINF)
- } /* End Method(_SB.INTF._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_PRS\n") */
- Return(PITF)
- } /* Method(_SB.INTF._PRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINF, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTF._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKF\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINF)
- } /* End Method(_SB.INTF._SRS) */
- } /* End Device(INTF) */
-
- Device(INTG) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 7)
-
- Method(_STA, 0) {
- if (PING) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTG._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKG\\_DIS\n") */
- Store(0, PING)
- } /* End Method(_SB.INTG._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PING, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTG._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKG\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PING)
- } /* End Method(_SB.INTG._SRS) */
- } /* End Device(INTG) */
-
- Device(INTH) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 8)
-
- Method(_STA, 0) {
- if (PINH) {
- Return(0x0B) /* sata is invisible */
- } else {
- Return(0x09) /* sata is disabled */
- }
- } /* End Method(_SB.INTH._STA) */
-
- Method(_DIS ,0) {
- /* DBGO("\\_SB\\LNKH\\_DIS\n") */
- Store(0, PINH)
- } /* End Method(_SB.INTH._DIS) */
-
- Method(_PRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_PRS\n") */
- Return(IRQP)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_CRS ,0) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(IRQB, 0x1, IRQN)
- ShiftLeft(1, PINH, IRQN)
- Return(IRQB)
- } /* Method(_SB.INTH._CRS) */
-
- Method(_SRS, 1) {
- /* DBGO("\\_SB\\LNKH\\_CRS\n") */
- CreateWordField(ARG0, 1, IRQM)
-
- /* Use lowest available IRQ */
- FindSetRightBit(IRQM, Local0)
- if (Local0) {
- Decrement(Local0)
- }
- Store(Local0, PINH)
- } /* End Method(_SB.INTH._SRS) */
- } /* End Device(INTH) */
-
- } /* End Scope(_SB) */
-
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- \_SB.PCI0.SIOS (Arg0)
- } /* End Method(\_PTS) */
-
- /*
- * The following method results in a "not a valid reserved NameSeg"
- * warning so I have commented it out for the duration. It isn't
- * used, so it could be removed.
- *
- *
- * \_GTS OEM Going To Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- *
- * Method(\_GTS, 1) {
- * DBGO("\\_GTS\n")
- * DBGO("From S0 to S")
- * DBGO(Arg0)
- * DBGO("\n")
- * }
- */
-
- /*
- * \_BFS OEM Back From Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * -none-
- */
- Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
- }
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- Store(1,HPDE)
-
- /* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
-
- /* if (DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
- * } else {
- * Store(Arg0, Index(WKST,1))
- * }
- */
- \_SB.PCI0.SIOW ()
- Return(WKST)
- } /* End Method(\_WAK) */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* General event 0 */
- /* Method(_L00) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 1 */
- /* Method(_L01) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 2 */
- /* Method(_L02) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* General event 4 */
- /* Method(_L04) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 5 */
- /* Method(_L05) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 6 - Used for GPM6, moved to USB.asl */
- /* Method(_L06) {
- * DBGO("\\_GPE\\_L00\n")
- * }
- */
-
- /* General event 7 - Used for GPM7, moved to USB.asl */
- /* Method(_L07) {
- * DBGO("\\_GPE\\_L07\n")
- * }
- */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- Notify (\_TZ.TZ00, 0x80)
- }
-
- /* Reserved */
- /* Method(_L0A) {
- * DBGO("\\_GPE\\_L0A\n")
- * }
- */
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* AC97 controller PME# */
- /* Method(_L0C) {
- * DBGO("\\_GPE\\_L0C\n")
- * }
- */
-
- /* OtherTherm PME# */
- /* Method(_L0D) {
- * DBGO("\\_GPE\\_L0D\n")
- * }
- */
-
- /* GPM9 SCI event - Moved to USB.asl */
- /* Method(_L0E) {
- * DBGO("\\_GPE\\_L0E\n")
- * }
- */
-
- /* PCIe HotPlug event */
- /* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
- * }
- */
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* PCIe PME# event */
- /* Method(_L12) {
- * DBGO("\\_GPE\\_L12\n")
- * }
- */
-
- /* GPM0 SCI event - Moved to USB.asl */
- /* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
- * }
- */
-
- /* GPM1 SCI event - Moved to USB.asl */
- /* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
- * }
- */
-
- /* GPM2 SCI event - Moved to USB.asl */
- /* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
- * }
- */
-
- /* GPM3 SCI event - Moved to USB.asl */
- /* Method(_L16) {
- * DBGO("\\_GPE\\_L16\n")
- * }
- */
-
- /* GPM8 SCI event - Moved to USB.asl */
- /* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
- * }
- */
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM4 SCI event - Moved to USB.asl */
- /* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
- * }
- */
-
- /* GPM5 SCI event - Moved to USB.asl */
- /* Method(_L1A) {
- * DBGO("\\_GPE\\_L1A\n")
- * }
- */
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* GPM6 SCI event - Reassigned to _L06 */
- /* Method(_L1C) {
- * DBGO("\\_GPE\\_L1C\n")
- * }
- */
-
- /* GPM7 SCI event - Reassigned to _L07 */
- /* Method(_L1D) {
- * DBGO("\\_GPE\\_L1D\n")
- * }
- */
-
- /* GPIO2 or GPIO66 SCI event */
- /* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
- * }
- */
-
- /* SATA SCI event - Moved to sata.asl */
- /* Method(_L1F) {
- * DBGO("\\_GPE\\_L1F\n")
- * }
- */
-
- } /* End Scope GPE */
-
- #include "acpi/usb.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
- /* _SB.PCI0 */
- /* Note: Only need HID on Primary Bus */
- Device(PCI0) {
- External (TOM1)
- External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
- Name(_HID, EISAID("PNP0A03"))
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
- Method(_BBN, 0) { /* Bus number = 0 */
- Return(0)
- }
- Method(_STA, 0) {
- /* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
- }
-
- Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
- } /* end _PRT */
-
- /* Describe the Northbridge devices */
- Device(AMRT) {
- Name(_ADR, 0x00000000)
- } /* end AMRT */
-
- /* The internal GFX bridge */
- Device(AGPB) {
- Name(_ADR, 0x00010000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- Return (APR1)
- }
- } /* end AGPB */
-
- /* The external GFX bridge */
- Device(PBR2) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
- Return (PS2) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR2 */
-
- /* Dev3 is also an external GFX bridge, not used in Herring */
-
- Device(PBR4) {
- Name(_ADR, 0x00040000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR4 */
-
- Device(PBR5) {
- Name(_ADR, 0x00050000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR5 */
-
- Device(PBR6) {
- Name(_ADR, 0x00060000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR6 */
-
- /* The onboard EtherNet chip */
- Device(PBR7) {
- Name(_ADR, 0x00070000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR7 */
-
- /* GPP */
- Device(PBR9) {
- Name(_ADR, 0x00090000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS9) } /* APIC mode */
- Return (PS9) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR9 */
-
- Device(PBRa) {
- Name(_ADR, 0x000A0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSa) } /* APIC mode */
- Return (PSa) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRa */
-
- Device(PBRb) {
- Name(_ADR, 0x000b0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSb) } /* APIC mode */
- Return (PSb) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRb */
-
- Device(PBRc) {
- Name(_ADR, 0x000c0000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APSc) } /* APIC mode */
- Return (PSc) /* PIC Mode */
- } /* end _PRT */
- } /* end PBRc */
-
-
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
- Name(_PRW, Package() {0x18, 4})
-
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
-
- /* Describe the Southbridge devices */
- Device(STCR) {
- Name(_ADR, 0x00110000)
- #include "acpi/sata.asl"
- } /* end STCR */
-
- Device(UOH1) {
- Name(_ADR, 0x00130000)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH1 */
-
- Device(UOH2) {
- Name(_ADR, 0x00130001)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH2 */
-
- Device(UOH3) {
- Name(_ADR, 0x00130002)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH3 */
-
- Device(UOH4) {
- Name(_ADR, 0x00130003)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH4 */
-
- Device(UOH5) {
- Name(_ADR, 0x00130004)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UOH5 */
-
- Device(UEH1) {
- Name(_ADR, 0x00130005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(SBUS) {
- Name(_ADR, 0x00140000)
- } /* end SBUS */
-
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- #include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
- Name(_ADR, 0x00140002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6C),
- MMDT, 16,
- }
-
- Method(_INI) {
- If(LEqual(OSVR,3)){ /* If we are running Linux */
- Store(zero, NSEN)
- Store(one, NSDO)
- Store(one, NSDI)
- }
- }
- } /* end AZHD */
-
- Device(LIBR) {
- Name(_ADR, 0x00140003)
- /* Method(_INI) {
- * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
- } */ /* End Method(_SB.SBRDG._INI) */
-
- /* Real Time Clock Device */
- Device(RTC0) {
- Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){8}
- IO(Decode16,0x0070, 0x0070, 0, 2)
- /* IO(Decode16,0x0070, 0x0070, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
- Device(TMR) { /* Timer */
- Name(_HID,EISAID("PNP0100")) /* System Timer */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){0}
- IO(Decode16, 0x0040, 0x0040, 0, 4)
- /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
- Device(SPKR) { /* Speaker */
- Name(_HID,EISAID("PNP0800")) /* AT style speaker */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0061, 0x0061, 0, 1)
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
- Device(PIC) {
- Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags(){2}
- IO(Decode16,0x0020, 0x0020, 0, 2)
- IO(Decode16,0x00A0, 0x00A0, 0, 2)
- /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
- /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
- Device(MAD) { /* 8257 DMA */
- Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
- Name(_CRS, ResourceTemplate() {
- DMA(Compatibility,BusMaster,Transfer8){4}
- IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
- IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
- IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
- IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
- IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
- IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
- }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
- } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
- Device(COPR) {
- Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
- IRQNoFlags(){13}
- })
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
- Device(HPTM) {
- Name(_HID,EISAID("PNP0103"))
- Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
- })
- Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
- }
- Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBX)
- Store(HPBA, HPBX)
- Return(CRS)
- }
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- } /* end LIBR */
-
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
-
- /* ITE8718 Support */
- OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
- Field (IOID, ByteAcc, NoLock, Preserve)
- {
- SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
- }
-
- IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
- {
- Offset (0x07),
- LDN, 8, /* Logical Device Number */
- Offset (0x20),
- CID1, 8, /* Chip ID Byte 1, 0x87 */
- CID2, 8, /* Chip ID Byte 2, 0x12 */
- Offset (0x30),
- ACTR, 8, /* Function activate */
- Offset (0xF0),
- APC0, 8, /* APC/PME Event Enable Register */
- APC1, 8, /* APC/PME Status Register */
- APC2, 8, /* APC/PME Control Register 1 */
- APC3, 8, /* Environment Controller Special Configuration Register */
- APC4, 8 /* APC/PME Control Register 2 */
- }
-
- /* Enter the 8718 MB PnP Mode */
- Method (EPNP)
- {
- Store(0x87, SIOI)
- Store(0x01, SIOI)
- Store(0x55, SIOI)
- Store(0x55, SIOI) /* 8718 magic number */
- }
- /* Exit the 8718 MB PnP Mode */
- Method (XPNP)
- {
- Store (0x02, SIOI)
- Store (0x02, SIOD)
- }
- /*
- * Keyboard PME is routed to SB700 Gevent3. We can wake
- * up the system by pressing the key.
- */
- Method (SIOS, 1)
- {
- /* We only enable KBD PME for S5. */
- If (LLess (Arg0, 0x05))
- {
- EPNP()
- /* DBGO("8718F\n") */
-
- Store (0x4, LDN)
- Store (One, ACTR) /* Enable EC */
- /*
- Store (0x4, LDN)
- Store (0x04, APC4)
- */ /* falling edge. which mode? Not sure. */
-
- Store (0x4, LDN)
- Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
- Store (0x4, LDN)
- Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
- XPNP()
- }
- }
- Method (SIOW, 0)
- {
- EPNP()
- Store (0x4, LDN)
- Store (Zero, APC0) /* disable keyboard PME */
- Store (0x4, LDN)
- Store (0xFF, APC1) /* clear keyboard PME status */
- XPNP()
- }
-
- Name(CRES, ResourceTemplate() {
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
-#if 0
- Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
-
- /* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
-
- /* BIOS space just below 4GB */
- DWORDMemory(
- ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PCBM
- )
-
- /* DRAM memory from 4GB to TopMem2 */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- DMHI
- )
-
- /* BIOS space just below 16EB */
- QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Granularity */
- 0x00000000, /* Min */
- 0x00000000, /* Max */
- 0x00000000, /* Translation */
- 0x00000001, /* Max-Min, RLEN */
- ,,
- PEBM
- )
-#endif
-
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
- }) /* End Name(_SB.PCI0.CRES) */
-
- Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
-#if 0
- CreateDWordField(CRES, ^EMM1._BAS, EM1B)
- CreateDWordField(CRES, ^EMM1._LEN, EM1L)
- CreateDWordField(CRES, ^DMLO._BAS, DMLB)
- CreateDWordField(CRES, ^DMLO._LEN, DMLL)
- CreateDWordField(CRES, ^PCBM._MIN, PBMB)
- CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
- CreateQWordField(CRES, ^DMHI._MIN, DMHB)
- CreateQWordField(CRES, ^DMHI._LEN, DMHL)
- CreateQWordField(CRES, ^PEBM._MIN, EBMB)
- CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
- If(LGreater(LOMH, 0xC0000)){
- Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
- Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
- }
-
- /* Set size of memory from 1MB to TopMem */
- Subtract(TOM1, 0x100000, DMLL)
-
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB) /* Reserve the "BIOS" space */
- Store(PBLN,PBML)
- }
- Else { /* Otherwise, put the BIOS just below 16EB */
- ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
-#endif
-
- CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
-
- Return(CRES) /* note to change the Name buffer */
- } /* end of Method(_SB.PCI0._CRS) */
-
- /*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
- Method(_INI, 0) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
- * }
- */
- } /* End Method(_SB._INI) */
- } /* End Device(PCI0) */
-
- Device(PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- } /* End \_SB scope */
-
- Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
- } /* End Scope SI */
-
- #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
- /* THERMAL */
- Scope(\_TZ) {
- Name (KELV, 2732)
- Name (THOT, 800)
- Name (TCRT, 850)
-
- ThermalZone(TZ00) {
- Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
- /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
- Return(Add(0, 2730))
- }
- Method(_AL0,0) { /* Returns package of cooling device to turn on */
- /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
- Return(Package() {\_TZ.TZ00.FAN0})
- }
- Device (FAN0) {
- Name(_HID, EISAID("PNP0C0B"))
- Name(_PR0, Package() {PFN0})
- }
-
- PowerResource(PFN0,0,0) {
- Method(_STA) {
- Store(0xF,Local0)
- Return(Local0)
- }
- Method(_ON) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
- }
- Method(_OFF) {
- /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
- }
- }
-
- Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
- Return (Add (THOT, KELV))
- }
- Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
- /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
- Return (Add (TCRT, KELV))
- }
- Method(_TMP,0) { /* return current temp of this zone */
- Store (SMBR (0x07, 0x4C,, 0x00), Local0)
- If (LGreater (Local0, 0x10)) {
- Store (Local0, Local1)
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400, KELV))
- }
-
- Store (SMBR (0x07, 0x4C, 0x01), Local0)
- /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
- /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
- If (LGreater (Local0, 0x10)) {
- If (LGreater (Local0, Local1)) {
- Store (Local0, Local1)
- }
-
- Multiply (Local1, 10, Local1)
- Return (Add (Local1, KELV))
- }
- Else {
- Add (Local0, THOT, Local0)
- Return (Add (400 , KELV))
- }
- } /* end of _TMP */
- } /* end of TZ00 */
- }
-}
-/* End of ASL file */
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
deleted file mode 100644
index 8bc96c22a8..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_sr5650[14];
-
-void get_bus_conf(void)
-{
- struct device *dev;
- int i;
-
- get_default_pci1234(1);
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
-
- for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
- bus_sr5650[i] = 0;
- }
-
-
- bus_sr5650[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- pirq_router_bus = bus_sr5650[0];
-
- /* sr5650 */
- for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
- dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sysconf.sbdn + i, 0));
- if (dev) {
- bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_sr5650[i]) {
- }
- }
- }
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/irq_tables.c b/src/mainboard/supermicro/h8scm_fam10/irq_tables.c
deleted file mode 100644
index 81fae72956..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/irq_tables.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = pirq_router_bus;
- pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, pirq_router_bus,
- PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2,
- 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
deleted file mode 100644
index b16f7a24d1..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sr5650/cmn.h>
-
-/*
- * TODO: Add the routine info of each PCIE_RESET_L.
- * TODO: Add the reset of each PCIE_RESET_L.
- * PCIE_RESET_GPIO1 -> Slot 0
- * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709
- * PCIE_RESET_GPIO3 -> TMS
- * PCIE_RESET_GPIO4 -> Slot 1
- * PCIE_RESET_GPIO5 -> Slot 2
- ***/
-void set_pcie_reset(void)
-{
- struct device *pcie_core_dev;
-
- pcie_core_dev = pcidev_on_root(0, 0);
- set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
- set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
-}
-
-void set_pcie_dereset(void)
-{
- struct device *pcie_core_dev;
-
- pcie_core_dev = pcidev_on_root(0, 0);
- set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
- set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
-}
-
-/*************************************************
-* enable the dedicated function in h8scm board.
-* This function called early than sr5650_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
-
- msr_t msr, msr2;
-
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk
- (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h
deleted file mode 100644
index 59861163c9..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- u8 bus_isa;
- u8 bus_8132_0;
- u8 bus_8132_1;
- u8 bus_8132_2;
- u8 bus_8111_0;
- u8 bus_8111_1;
- u8 bus_8132a[31][3];
- u8 bus_8151[31][2];
-
- u32 apicid_8111;
- u32 apicid_8132_1;
- u32 apicid_8132_2;
- u32 apicid_8132a[31][2];
- u32 sbdn3;
- u32 sbdn3a[31];
- u32 sbdn5[31];
-};
-
-#endif
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
deleted file mode 100644
index 112d20ae41..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern u8 bus_sr5650[14];
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u32 apicid_sp5100;
- u32 apicid_sr5650;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- apicid_sp5100 = 0x20;
- apicid_sr5650 = apicid_sp5100 + 1;
-
- mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- u32 *dword;
- u8 byte;
-
- dev = pcidev_on_root(0x14, 0);
- if (dev) {
- dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
- smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
-
- /* Initialize interrupt mapping */
- /* aza */
- byte = pci_read_config8(dev, 0x63);
- byte &= 0xf8;
- byte |= 0; /* 0: INTA, ...., 7: INTH */
- pci_write_config8(dev, 0x63, byte);
-
- /* SATA */
- dword = (u32 *)((pci_read_config32(dev, 0xac) &
- ~(7 << 26)) | (6 << 26));
-
- /* dword |= 1 << 22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, (u32)dword);
-
- /*
- * 00:12.0: PROG SATA : INT F
- * 00:13.0: INTA USB_0
- * 00:13.1: INTB USB_1
- * 00:13.2: INTC USB_2
- * 00:13.3: INTD USB_3
- * 00:13.4: INTC USB_4
- * 00:13.5: INTD USB2
- * 00:14.1: INTA IDE
- * 00:14.2: Prog HDA : INT E
- * 00:14.5: INTB ACI
- * 00:14.6: INTB MCI
- */
- }
- dev = pcidev_on_root(0, 0);
- if (dev) {
- pci_write_config32(dev, 0xF8, 0x1);
- dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
- smp_write_ioapic(mc, apicid_sr5650, 0x11, dword);
- }
- }
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
-
- /* on board NIC & Slot PCIE. */
- /* configuration B doesnt need dev 5,6,7 */
- /*
- * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
- * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
- * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
- */
- smp_write_pci_intsrc(mc, mp_INT, 0, 2, 0, apicid_sr5650, 28); /* dev 2 */
- smp_write_pci_intsrc(mc, mp_INT, 0, 4, 0, apicid_sr5650, 28); /* dev 4 */
- smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 11 */
- smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 12 */
-
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[2], 0, 0, apicid_sr5650, 0); /* card behind dev2 */
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 0, apicid_sr5650, 20);
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 1, apicid_sr5650, 21); /* NIC */
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 0, apicid_sr5650, 8);
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 1, apicid_sr5650, 9); /* card behind dev11 */
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 0, apicid_sr5650, 12);
- smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 1, apicid_sr5650, 13); /* card behind dev12 */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c
deleted file mode 100644
index 80d2d9d05c..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
-// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
- ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
- ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
- ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
- ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
- ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
- ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
- ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
-// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
- ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
- ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp address bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
- ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
- ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-// ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
- ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-// ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
- ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
- ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
- ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
- ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
-// ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
- ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
- ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
deleted file mode 100644
index 302e86f4e8..0000000000
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-//#define SYSTEM_TYPE 0 /* SERVER */ //FIXME SERVER enable ECC, cause linux hang
-#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/car.h>
-#include <southbridge/amd/common/reset.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <southbridge/amd/sr5650/sr5650.h>
-#include <superio/nuvoton/wpcm450/wpcm450.h>
-#include <spd.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-
-#include "cpu/amd/quadcore/quadcore.c"
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-
-int spd_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = get_sysinfo();
- static const u8 spd_addr[] = {
- RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0,
- //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,
- };
- u32 bsp_apicid = 0;
- u32 val;
- msr_t msr;
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- /* mov bsp to bus 0xff when > 8 nodes */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
-
- /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
- * disable all pcie bridges on SR56x0 to work around it
- */
- sr5650_disable_pcie_bridge();
- sb7xx_51xx_lpc_port80();
- }
-
- post_code(0x30);
-
- if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
- /* All cores run this but the BSP(node0,core0) is the only core that returns. */
- }
-
- post_code(0x32);
-
- enable_sr5650_dev8();
- sb7xx_51xx_lpc_init();
-
- sb7xx_51xx_enable_wideio(0, 0x1600);
-
- wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
-
- sb7xx_51xx_disable_wideio(0);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- // Load MPB
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- update_microcode(val);
-
- post_code(0x33);
-
- cpuSetAMDMSR(0);
- post_code(0x34);
-
- /* TODO: The Kernel must support 12 processor, otherwise the interrupt
- * can not work correctly. */
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- It would be nice to fixup prink spinlocks for ROM XIP mode.
- I think it could be done by putting the spinlock flag in the cache
- of the BSP located right after sysinfo.
- */
- wait_all_core0_started();
-
-#if CONFIG(LOGICAL_CPUS)
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores(bsp_apicid);
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- post_code(0x38);
-
- /* run _early_setup before soft-reset. */
- sr5650_early_setup();
- sb7xx_51xx_early_setup();
-
-#if CONFIG(SET_FIDVID)
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
- /* FIXME: The sb fid change may survive the warm reset and only
- need to be done once.*/
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
-
- post_code(0x3A);
-
- /* show final fid and vid */
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
-
- sr5650_htinit();
-
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset - shouldn't see this message!!!\n");
- }
-
- post_code(0x3B);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- post_code(0x40);
-
- raminit_amdmct(sysinfo);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- amdmct_cbmem_store_info(sysinfo);
-
- sr5650_before_pci_init();
- sb7xx_51xx_before_pci_init();
-
- post_code(0x42);
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] node = The node on which this chain is located
- * @param[in] link = The link on the host for this chain
- * @param[out] List = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
- }
-
- return 0;
-}