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-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/spd_addr.h83
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/spd_addr.h83
-rw-r--r--src/mainboard/supermicro/x6dai_g/debug.c12
-rw-r--r--src/mainboard/supermicro/x6dhe_g/debug.c12
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/debug.c12
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/debug.c12
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/debug.c12
7 files changed, 29 insertions, 197 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h b/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h
index a8abf331ee..40c5ac712a 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h
+++ b/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h
@@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/**
- * This file defines the SPD addresses for the mainboard. Must be included in
- * romstage.c
- */
-
-#define RC00 0
-#define RC01 1
-#define RC02 2
-#define RC03 3
-#define RC04 4
-#define RC05 5
-#define RC06 6
-#define RC07 7
-#define RC08 8
-#define RC09 9
-#define RC10 10
-#define RC11 11
-#define RC12 12
-#define RC13 13
-#define RC14 14
-#define RC15 15
-#define RC16 16
-#define RC17 17
-#define RC18 18
-#define RC19 19
-#define RC20 20
-#define RC21 21
-#define RC22 22
-#define RC23 23
-#define RC24 24
-#define RC25 25
-#define RC26 26
-#define RC27 27
-#define RC28 28
-#define RC29 29
-#define RC30 30
-#define RC31 31
-
-#define RC32 32
-#define RC33 33
-#define RC34 34
-#define RC35 35
-#define RC36 36
-#define RC37 37
-#define RC38 38
-#define RC39 39
-#define RC40 40
-#define RC41 41
-#define RC42 42
-#define RC43 43
-#define RC44 44
-#define RC45 45
-#define RC46 46
-#define RC47 47
-#define RC48 48
-#define RC49 49
-#define RC50 50
-#define RC51 51
-#define RC52 52
-#define RC53 53
-#define RC54 54
-#define RC55 55
-#define RC56 56
-#define RC57 57
-#define RC58 58
-#define RC59 59
-#define RC60 60
-#define RC61 61
-#define RC62 62
-#define RC63 63
-
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+/** This file defines the SPD addresses for the mainboard. */
+#include <spd.h>
static const u8 spd_addr[] = {
//first node
@@ -107,4 +29,3 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};
-
diff --git a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
index 5b32b4c2d6..1bcf039198 100644
--- a/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
+++ b/src/mainboard/supermicro/h8qme_fam10/spd_addr.h
@@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/**
- * This file defines the SPD addresses for the mainboard. Must be included in
- * romstage.c
- */
-
-#define RC00 0
-#define RC01 1
-#define RC02 2
-#define RC03 3
-#define RC04 4
-#define RC05 5
-#define RC06 6
-#define RC07 7
-#define RC08 8
-#define RC09 9
-#define RC10 10
-#define RC11 11
-#define RC12 12
-#define RC13 13
-#define RC14 14
-#define RC15 15
-#define RC16 16
-#define RC17 17
-#define RC18 18
-#define RC19 19
-#define RC20 20
-#define RC21 21
-#define RC22 22
-#define RC23 23
-#define RC24 24
-#define RC25 25
-#define RC26 26
-#define RC27 27
-#define RC28 28
-#define RC29 29
-#define RC30 30
-#define RC31 31
-
-#define RC32 32
-#define RC33 33
-#define RC34 34
-#define RC35 35
-#define RC36 36
-#define RC37 37
-#define RC38 38
-#define RC39 39
-#define RC40 40
-#define RC41 41
-#define RC42 42
-#define RC43 43
-#define RC44 44
-#define RC45 45
-#define RC46 46
-#define RC47 47
-#define RC48 48
-#define RC49 49
-#define RC50 50
-#define RC51 51
-#define RC52 52
-#define RC53 53
-#define RC54 54
-#define RC55 55
-#define RC56 56
-#define RC57 57
-#define RC58 58
-#define RC59 59
-#define RC60 60
-#define RC61 61
-#define RC62 62
-#define RC63 63
-
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+/** This file defines the SPD addresses for the mainboard. */
+#include <spd.h>
static const u8 spd_addr[] = {
//first node
@@ -113,4 +35,3 @@ static const u8 spd_addr[] = {
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};
-
diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c
index 87c67b5964..93199d7b8a 100644
--- a/src/mainboard/supermicro/x6dai_g/debug.c
+++ b/src/mainboard/supermicro/x6dai_g/debug.c
@@ -1,6 +1,4 @@
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x57
-#define SMBUS_MEM_DEVICE_INC 1
+#include <spd.h>
static void print_reg(unsigned char index)
{
@@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
@@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c
index 87c67b5964..93199d7b8a 100644
--- a/src/mainboard/supermicro/x6dhe_g/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g/debug.c
@@ -1,6 +1,4 @@
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x57
-#define SMBUS_MEM_DEVICE_INC 1
+#include <spd.h>
static void print_reg(unsigned char index)
{
@@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
@@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c
index 87c67b5964..93199d7b8a 100644
--- a/src/mainboard/supermicro/x6dhe_g2/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g2/debug.c
@@ -1,6 +1,4 @@
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x57
-#define SMBUS_MEM_DEVICE_INC 1
+#include <spd.h>
static void print_reg(unsigned char index)
{
@@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
@@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c
index 87c67b5964..93199d7b8a 100644
--- a/src/mainboard/supermicro/x6dhr_ig/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig/debug.c
@@ -1,6 +1,4 @@
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x57
-#define SMBUS_MEM_DEVICE_INC 1
+#include <spd.h>
static void print_reg(unsigned char index)
{
@@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
@@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c
index 87c67b5964..93199d7b8a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c
@@ -1,6 +1,4 @@
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x57
-#define SMBUS_MEM_DEVICE_INC 1
+#include <spd.h>
static void print_reg(unsigned char index)
{
@@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
@@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
print_debug("\n");
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 22:18:57 +0000