11 files changed, 9 insertions, 29 deletions

diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig
index 219b82a1d0..221ccb2dbf 100644
--- a/src/mainboard/supermicro/h8dme/Kconfig
+++ b/src/mainboard/supermicro/h8dme/Kconfig
@@ -36,10 +36,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10
diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c
index 2e9c5a9029..4717e24e5a 100644
--- a/src/mainboard/supermicro/h8dme/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dme/ap_romstage.c
@@ -65,8 +65,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 6f156bc39f..84771781c3 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -178,8 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		RC1 | DIMM5, RC1 | DIMM7,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
 
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig
index 9fd8c7ccf8..3cc296a985 100644
--- a/src/mainboard/supermicro/h8dmr/Kconfig
+++ b/src/mainboard/supermicro/h8dmr/Kconfig
@@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x01000
-
 config APIC_ID_OFFSET
 	hex
 	default 0x10
diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c
index d04775bba3..d577061cd5 100644
--- a/src/mainboard/supermicro/h8dmr/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c
@@ -65,8 +65,8 @@ static inline unsigned get_nodes(void)
 
 void hardwaremain(int ret_addr)
 {
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
-        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+	struct sys_info *sysinfo = &sysinfo_car; // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM
 
 	struct node_core_id id;
 
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index e3113d85dc..62cbf0f7ec 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -107,8 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		DIMM5, DIMM7, 0, 0,
 	};
 
-        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = &sysinfo_car;
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
index 20a0082b44..94b56eaa1d 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig
@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index be5a8e1874..b01cd03ed9 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -109,8 +109,7 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
-		CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val, wants_reset;
 	msr_t msr;
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig
index 134a25ebc6..6ba6130119 100644
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig
@@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x0c000
 
-config DCACHE_RAM_GLOBAL_VAR_SIZE
-	hex
-	default 0x04000
-
 config RAMBASE
 	hex
 	default 0x200000
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 28efb1cf87..aa65a96540 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -160,8 +160,7 @@ static void write_GPIO(void)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
-		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	u32 bsp_apicid = 0, val, wants_reset;
 	msr_t msr;
 
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 6ad1484462..7aac4afd45 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -86,7 +86,7 @@ static int spd_read_byte(u32 device, u32 address)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = &sysinfo_car;
 	static const u8 spd_addr[] = {
 				RC00, 0x52,  0x53,  0, 0, 0x50,  0x51,  0, 0,
 				//RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,