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-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c16
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c4
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8qgi/romstage.c8
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8scm/romstage.c8
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c2
7 files changed, 17 insertions, 25 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 21355634ab..3edd0930f0 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -146,9 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
- print_debug("bsp_apicid=");
- print_debug_hex8(bsp_apicid);
- print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#if CONFIG_DEBUG_SMBUS
@@ -174,10 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr = rdmsr(0xc0010042);
- print_debug("begin msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -186,10 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr = rdmsr(0xc0010042);
- print_debug("end msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -201,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 84198d2168..1675427c74 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index a6bb53c35c..d185653d83 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 07c3c3375e..ef0374e58f 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -107,14 +107,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 3fdd254340..72ca8b68c0 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -269,7 +269,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index ed82a38135..1f7fb420dd 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -101,14 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index dc5b2964e5..eb38a29bca 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -196,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}