summaryrefslogtreecommitdiff
path: root/src/mainboard/technexion/tim8690
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/technexion/tim8690')
-rw-r--r--src/mainboard/technexion/tim8690/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index ed133daf6e..4453f84455 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = &sysinfo_car;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */