diff options
Diffstat (limited to 'src/mainboard/tyan/s2850')
| -rw-r--r-- | src/mainboard/tyan/s2850/romstage.c | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 41a4ffa79f..4f78797030 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -29,28 +29,23 @@ static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } } -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -86,16 +81,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); } - if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - } // post_code(0x32); @@ -128,4 +119,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } - |