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-rw-r--r--src/mainboard/tyan/s2875/mptable.c4
-rw-r--r--src/mainboard/tyan/s2875/romstage.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index c3765f2da1..90299a746b 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -98,7 +98,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 832255c684..4b52cd37b6 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif