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-rw-r--r--src/mainboard/tyan/s2881/Config.lb374
1 files changed, 184 insertions, 190 deletions
diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb
index 69be43eb0f..3bdbfa4fe7 100644
--- a/src/mainboard/tyan/s2881/Config.lb
+++ b/src/mainboard/tyan/s2881/Config.lb
@@ -1,220 +1,214 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
driver mainboard.o
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#dir /drivers/broadcom/tg3_ipmi
-dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
-#
-#### Should this be in the northbridge code?
+
+### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
+
+##
+## Include an id string (For safe flashing)
+##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
+
###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-#
if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-#
-#
-###
-### Setup the serial port
###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### Romcc output
+### O.k. We aren't just an intermediary anymore!
###
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
-
-makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
-end
-mainboardinit cpu/k8/enable_mmx_sse.inc
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files
-###
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+##
+## Include the secondary Configuration files
+##
dir /pc80
+config chip.h
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 2
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 2
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
-end
-
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
-
+# sample config for tyan/s2881
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
-#dir /bioscall
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
end
-cpu k8 "cpu1"
-end