1 files changed, 0 insertions, 121 deletions
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
deleted file mode 100644
index fdf9606c47..0000000000
--- a/src/mainboard/tyan/s2885/romstage.c
+++ /dev/null
@@ -1,121 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/early_ctrl.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0())
-        outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   else
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const uint16_t spd_addr [] = {
-			DIMM0, DIMM2, 0, 0,
-			DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-			DIMM4, DIMM6, 0, 0,
-			DIMM5, DIMM7, 0, 0,
-#endif
-	};
-
-        int needs_reset;
-        unsigned bsp_apicid = 0, nodes;
-        struct mem_controller ctrl[8];
-
-        if (bist == 0)
-                bsp_apicid = init_cpus(cpu_init_detectedx);
-
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s2885_resource_map();
-#if 0
-        dump_pci_device(PCI_DEV(0, 0x18, 0));
-	dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
-
-	needs_reset = setup_coherent_ht_domain();
-
-        wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
-        // It is said that we should start core1 after all core0 launched
-        start_other_cores();
-        wait_all_other_cores_started(bsp_apicid);
-#endif
-
-        needs_reset |= ht_setup_chains_x();
-
-       	if (needs_reset) {
-               	printk(BIOS_INFO, "ht reset -\n");
-               	soft_reset();
-       	}
-
-        allow_all_aps_stop(bsp_apicid);
-
-        nodes = get_nodes();
-        //It's the time to set ctrl now;
-        fill_mem_ctrl(nodes, ctrl, spd_addr);
-
-        enable_smbus();
-
-        memreset_setup();
-        sdram_initialize(nodes, ctrl);
-
-#if 0
-	dump_pci_devices();
-#endif
-
-	post_cache_as_ram();
-}