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Diffstat (limited to 'src/mainboard/tyan/s2892/auto.c')
-rw-r--r--src/mainboard/tyan/s2892/auto.c56
1 files changed, 27 insertions, 29 deletions
diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c
index 917fb8414a..3bd9209f09 100644
--- a/src/mainboard/tyan/s2892/auto.c
+++ b/src/mainboard/tyan/s2892/auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@@ -33,20 +33,20 @@
static void hard_reset(void)
{
- set_bios_reset();
+ set_bios_reset();
- /* full reset */
+ /* full reset */
outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
+ outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
- set_bios_reset();
+ set_bios_reset();
#if 1
- /* link reset */
+ /* link reset */
outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
+ outb(0x06, 0x0cf9);
#endif
}
@@ -73,10 +73,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
- /* tyan does not want the default */
-#include "resourcemap.c"
+/* tyan does not want the default */
+#include "resourcemap.c"
-#define FIRST_CPU 1
+#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -84,14 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
@@ -119,32 +118,31 @@ static void main(unsigned long bist)
#endif
};
- int needs_reset;
+ int needs_reset;
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
+ if (bist == 0) {
+ k8_init_and_stop_secondaries();
+ }
-
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
+ uart_init();
+ console_init();
+
/* Halt if there was a built in self test failure */
// report_bist_failure(bist);
- setup_s2892_resource_map();
+ setup_s2892_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
enable_smbus();