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-rw-r--r--src/mainboard/tyan/s2895/Config.lb76
-rw-r--r--src/mainboard/tyan/s2895/Options.lb43
-rw-r--r--src/mainboard/tyan/s2895/auto.c4
-rw-r--r--src/mainboard/tyan/s2895/cache_as_ram_auto.c110
-rw-r--r--src/mainboard/tyan/s2895/cmos.layout8
-rw-r--r--src/mainboard/tyan/s2895/get_bus_conf.c43
-rw-r--r--src/mainboard/tyan/s2895/irq_tables.c9
-rw-r--r--src/mainboard/tyan/s2895/mptable.c13
-rw-r--r--src/mainboard/tyan/s2895/resourcemap.c12
9 files changed, 221 insertions, 97 deletions
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index 6b41829017..9afaf70d8f 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -2,12 +2,17 @@
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+if USE_FAILOVER_IMAGE
+ default ROM_SECTION_SIZE = FAILOVER_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+ else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
+ end
end
##
@@ -16,7 +21,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -31,10 +35,18 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-arch i386 end
+if USE_FAILOVER_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+ if USE_FALLBACK_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+ else
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+ end
+end
+arch i386 end
##
## Build the objects we have code for in this directory.
@@ -92,9 +104,16 @@ end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/entry16.inc
- ldscript /cpu/x86/16bit/entry16.lds
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
end
mainboardinit cpu/x86/32bit/entry32.inc
@@ -113,12 +132,22 @@ end
##
## Build our reset vector (This is where linuxBIOS is entered)
##
-if USE_FALLBACK_IMAGE
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
+ end
end
if USE_DCACHE_RAM
@@ -136,13 +165,18 @@ ldscript /southbridge/nvidia/ck804/id.lds
##
## ROMSTRAP table for CK804
##
-if USE_FALLBACK_IMAGE
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit southbridge/nvidia/ck804/romstrap.inc
+ ldscript /southbridge/nvidia/ck804/romstrap.lds
+ end
end
-
-
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
@@ -155,12 +189,20 @@ end
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover_failover.lds
+ end
+ end
+else
+ if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
else
- mainboardinit ./failover.inc
+ mainboardinit ./failover.inc
end
+ end
end
##
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index cd367ad029..b1ee5367e8 100644
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -2,6 +2,8 @@ uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
+uses USE_FAILOVER_IMAGE
+uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
@@ -11,6 +13,7 @@ uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
+uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
@@ -60,6 +63,8 @@ uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
+uses SERIAL_CPU_INIT
+
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
@@ -69,28 +74,34 @@ uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_LB_MEM_TOPK
+
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
-#default ROM_SIZE=524288
+default ROM_SIZE=524288
#1M bytes
-default ROM_SIZE=1048576
+#default ROM_SIZE=1048576
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
-#256K
-default FALLBACK_SIZE=0x40000
+#default FALLBACK_SIZE=0x40000
-###
-### Build options
-###
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
@@ -130,15 +141,14 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
+default SERIAL_CPU_INIT=0
+
#CHIP_NAME ?
#default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
-#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0
@@ -151,6 +161,9 @@ default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
#VGA
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
@@ -163,7 +176,7 @@ default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
-default ENABLE_APIC_EXT_ID=1
+default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=0
@@ -201,12 +214,12 @@ default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x00100000
##
## Load the payload from the ROM
@@ -220,8 +233,8 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32"
+default HOSTCC="gcc-4.0.2"
##
## Disable the gdb stub by default
diff --git a/src/mainboard/tyan/s2895/auto.c b/src/mainboard/tyan/s2895/auto.c
index 5bfc6bf680..8c11f30fa7 100644
--- a/src/mainboard/tyan/s2895/auto.c
+++ b/src/mainboard/tyan/s2895/auto.c
@@ -13,7 +13,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/cpu_rev.c"
//#define K8_HT_FREQ_1G_SUPPORT 1
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
@@ -23,7 +23,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_msr.h>
+#include "cpu/amd/model_fxx/model_fxx_msr.h"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
index 299f345b71..576bebebfa 100644
--- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -6,7 +6,7 @@
//#define K8_SCAN_PCI_BUS 1
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
@@ -21,30 +21,53 @@
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
+#if 0
+static void post_code(uint8_t value) {
+#if 1
+ int i;
+ for(i=0;i<0x8000;i++) {
+ outb(value, 0x80);
+ }
+#endif
+}
+#endif
+
#include <cpu/amd/model_fxx_rev.h>
+
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
+#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+
+#define SUPERIO_GPIO_IO_BASE 0x400
+
+#if USE_FAILOVER_IMAGE==0
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
-#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -58,9 +81,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
static void sio_gpio_setup(void){
@@ -94,6 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#define CK804_NUM 2
+#define CK804B_BUSN 0x80
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
@@ -116,8 +137,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
+#endif
-#if USE_FALLBACK_IMAGE == 1
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -133,7 +155,7 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
+ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
@@ -141,13 +163,14 @@ static void sio_setup(void)
dword |= (1<<29)|(1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-#if 1
+ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
+ dword |= (1<<16);
+ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
+
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-#endif
}
@@ -175,6 +198,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
+// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@@ -186,28 +210,43 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
+// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
+// post_code(0x25);
+#if HAVE_FAILOVER_BOOT==1
+ __asm__ volatile ("jmp __fallback_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ )
+#endif
;
}
#endif
-
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
-#if USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
+#if HAVE_FAILOVER_BOOT==1
+ #if USE_FAILOVER_IMAGE==1
+ failover_process(bist, cpu_init_detectedx);
+ #else
+ real_main(bist, cpu_init_detectedx);
+ #endif
+#else
+ #if USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+ #endif
+ real_main(bist, cpu_init_detectedx);
#endif
- real_main(bist, cpu_init_detectedx);
-
}
+#if USE_FAILOVER_IMAGE==0
+
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@@ -229,6 +268,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
+// post_code(0x32);
+
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@@ -236,15 +277,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- setup_s2895_resource_map();
+ sio_gpio_setup();
+
+ setup_mb_resource_map();
+#if 0
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x19, 0));
+#endif
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
+ wait_all_other_cores_started(bsp_apicid);
#endif
needs_reset |= ht_setup_chains_x();
@@ -253,7 +300,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) {
print_info("ht reset -\r\n");
- soft_reset();
+ // soft_reset();
}
allow_all_aps_stop(bsp_apicid);
@@ -263,9 +310,24 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
+#if 0
+ dump_spd_registers(&cpu[0]);
+#endif
+#if 0
+ dump_smbus_registers();
+#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
+#if 0
+ print_pci_devices();
+#endif
+
+#if 0
+ dump_pci_devices();
+#endif
+
post_cache_as_ram();
}
+#endif
diff --git a/src/mainboard/tyan/s2895/cmos.layout b/src/mainboard/tyan/s2895/cmos.layout
index 5eb88b9a5a..c1f3d75316 100644
--- a/src/mainboard/tyan/s2895/cmos.layout
+++ b/src/mainboard/tyan/s2895/cmos.layout
@@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c
index 3decafb71e..4d1451a92f 100644
--- a/src/mainboard/tyan/s2895/get_bus_conf.c
+++ b/src/mainboard/tyan/s2895/get_bus_conf.c
@@ -7,6 +7,8 @@
#include <cpu/amd/dualcore.h>
#endif
+#include <cpu/amd/amdk8_sysconf.h>
+
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@@ -31,8 +33,7 @@
unsigned apicid_8131_2;
unsigned apicid_ck804b;
-unsigned sblk;
-unsigned pci1234[] =
+unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@@ -44,9 +45,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] =
+unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@@ -68,25 +67,31 @@ void get_bus_conf(void)
{
unsigned apicid_base;
+ unsigned sbdn;
device_t dev;
+ int i;
+
+ if(get_bus_conf_done==1) return; //do it only once
+
+ get_bus_conf_done = 1;
- if(get_bus_conf_done==1) return; //do it only once
+ sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ for(i=0;i<sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
- get_bus_conf_done = 1;
+ get_sblk_pci1234();
- hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
-
- get_sblk_pci1234();
-
- sbdn = (hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sbdn = sysconf.sbdn;
- sbdn3 = (hcdn[1] & 0xff);
+ sbdn3 = (sysconf.hcdn[1] & 0xff);
- sbdnb = (hcdn[2] & 0xff); // first byte of second chain
+ sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain
-// bus_ck804_0 = node_link_to_bus(0, sblk);
- bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
+ bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
@@ -158,7 +163,7 @@ void get_bus_conf(void)
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
}
- bus_8131_0 = (pci1234[1] >> 16) & 0xff;
+ bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
@@ -187,8 +192,8 @@ void get_bus_conf(void)
/* CK804b */
- if(pci1234[2] & 0xf) { //if the second cpu is installed
- bus_ck804b_0 = (pci1234[2]>>16) & 0xff;
+ if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
+ bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
if (dev) {
diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c
index 5ed428ff9f..1779644c12 100644
--- a/src/mainboard/tyan/s2895/irq_tables.c
+++ b/src/mainboard/tyan/s2895/irq_tables.c
@@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@@ -44,10 +46,7 @@ extern unsigned char bus_ck804b_3;//d
extern unsigned char bus_ck804b_4;//e
extern unsigned char bus_ck804b_5;//f
-extern unsigned pci1234[];
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
@@ -58,11 +57,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
+ unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
@@ -98,7 +99,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
- if(pci1234[2] & 0xf) {
+ if(sysconf.pci1234[2] & 0xf) {
//second pci beidge
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
pirq_info++; slot_num++;
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index a41cbcd12f..2d9313ea08 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
@@ -25,10 +27,6 @@ extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned apicid_ck804b;
-extern unsigned pci1234[];
-
-extern unsigned sbdn;
-extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
@@ -38,6 +36,7 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "TYAN ";
static const char productid[12] = "S2895 ";
struct mp_config_table *mc;
+ unsigned sbdn;
unsigned char bus_num;
int i;
@@ -62,6 +61,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
get_bus_conf();
+ sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
@@ -83,6 +83,7 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
+ /* Initialize interrupt mapping*/
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
@@ -110,7 +111,7 @@ void *smp_write_config_table(void *v)
}
}
- if(pci1234[2] & 0xf) {
+ if(sysconf.pci1234[2] & 0xf) {
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
@@ -181,7 +182,7 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
}
- if(pci1234[2] & 0xf) {
+ if(sysconf.pci1234[2] & 0xf) {
//Onboard ck804b NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
diff --git a/src/mainboard/tyan/s2895/resourcemap.c b/src/mainboard/tyan/s2895/resourcemap.c
index f35252c085..9de9b2e107 100644
--- a/src/mainboard/tyan/s2895/resourcemap.c
+++ b/src/mainboard/tyan/s2895/resourcemap.c
@@ -3,7 +3,7 @@
*
*/
-static void setup_s2895_resource_map(void)
+static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
@@ -183,7 +183,7 @@ static void setup_s2895_resource_map(void)
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -253,10 +253,10 @@ static void setup_s2895_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */
+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 06:40:25 +0000