diff options
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10/Config.lb')
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/Config.lb | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb index b9f1a5f3d8..b39e917b75 100644 --- a/src/mainboard/tyan/s2912_fam10/Config.lb +++ b/src/mainboard/tyan/s2912_fam10/Config.lb @@ -81,7 +81,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -if USE_DCACHE_RAM makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c if CONFIG_USE_INIT @@ -98,8 +97,6 @@ if USE_DCACHE_RAM end end -end - if USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR @@ -129,7 +126,6 @@ end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -137,8 +133,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end - ## ## Build our reset vector (This is where coreboot is entered) @@ -182,12 +176,10 @@ else end end -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -196,29 +188,22 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end ## ## Include the secondary Configuration files |