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-rw-r--r--src/mainboard/tyan/s2912_fam10/Kconfig4
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c2
2 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 9a38836e6f..085148fcd3 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE
hex
default 0x0c000
-config DCACHE_RAM_GLOBAL_VAR_SIZE
- hex
- default 0x04000
-
config APIC_ID_OFFSET
hex
default 0
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 16d3c472bd..bc01aeaa8e 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -113,7 +113,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = &sysinfo_car;
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;