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-rw-r--r--src/mainboard/tyan/s4882/Config.lb2
-rw-r--r--src/mainboard/tyan/s4882/Options.lb14
-rw-r--r--src/mainboard/tyan/s4882/auto.c49
-rw-r--r--src/mainboard/tyan/s4882/cache_as_ram_auto.c51
-rw-r--r--src/mainboard/tyan/s4882/reset.c6
5 files changed, 87 insertions, 35 deletions
diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
index 95ef0464fe..18fec090cf 100644
--- a/src/mainboard/tyan/s4882/Config.lb
+++ b/src/mainboard/tyan/s4882/Config.lb
@@ -43,7 +43,7 @@ arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
+object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
index 56a2548228..0c5571aa07 100644
--- a/src/mainboard/tyan/s4882/Options.lb
+++ b/src/mainboard/tyan/s4882/Options.lb
@@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
@@ -31,9 +28,9 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
+uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
-uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
@@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_HARD_RESET=1
##
-## Funky hard reset implementation
-##
-default HARD_RESET_BUS=3
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
@@ -153,8 +143,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="s4882"
default MAINBOARD_VENDOR="Tyan"
+default MAINBOARD_PART_NUMBER="s4882"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
diff --git a/src/mainboard/tyan/s4882/auto.c b/src/mainboard/tyan/s4882/auto.c
index 21d459b6e4..e8d46e7961 100644
--- a/src/mainboard/tyan/s4882/auto.c
+++ b/src/mainboard/tyan/s4882/auto.c
@@ -26,26 +26,52 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ unsigned reg;
+
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ unsigned config_map;
+ config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ if ((((config_map >> 4) & 7) == node) &&
+ (((config_map >> 8) & 3) == link))
+ {
+ return (config_map >> 16) & 0xff;
+ }
+ }
+ return 0;
+}
+
static void hard_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
+
set_bios_reset();
/* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ pci_write_config8(dev, 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
-static void soft2_reset(void)
-{
set_bios_reset();
- pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+ pci_write_config8(dev, 0x47, 1);
}
static void memreset_setup(void)
@@ -73,6 +99,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
+ /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
@@ -194,7 +221,7 @@ static void main(unsigned long bist)
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
- id = get_node_core_id_x();
+ id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
@@ -213,7 +240,7 @@ static void main(unsigned long bist)
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
- if( id.nodeid != 0 )
+ if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
@@ -241,7 +268,7 @@ static void main(unsigned long bist)
|| (id.coreid != 0)
#endif
) {
- stop_this_cpu();
+ stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
@@ -257,10 +284,10 @@ static void main(unsigned long bist)
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
+ // It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
- // automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c
index bbcc49a9cf..234e3a0a58 100644
--- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c
@@ -37,20 +37,52 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ unsigned reg;
+
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ unsigned config_map;
+ config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ if ((((config_map >> 4) & 7) == node) &&
+ (((config_map >> 8) & 3) == link))
+ {
+ return (config_map >> 16) & 0xff;
+ }
+ }
+ return 0;
+}
+
static void hard_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
+
set_bios_reset();
/* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ pci_write_config8(dev, 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
+
set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+ pci_write_config8(dev, 0x47, 1);
}
static void memreset_setup(void)
@@ -77,6 +109,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
+ /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
@@ -109,6 +142,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
+#else
+#include "cpu/amd/model_fxx/node_id.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
@@ -325,7 +360,6 @@ void amd64_main(unsigned long bist)
distinguish_cpu_resets(nodeid);
#endif
-
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
@@ -337,22 +371,15 @@ void amd64_main(unsigned long bist)
}
}
-
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
- dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s4882_resource_map();
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
- dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
-
+
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
@@ -387,6 +414,7 @@ void amd64_main(unsigned long bist)
}
#endif
+#if 1
cpu_reset_x:
@@ -450,6 +478,7 @@ cpu_reset_x:
copy_and_run(new_cpu_reset);
/* We will not return */
}
+#endif
print_debug("should not be here -\r\n");
diff --git a/src/mainboard/tyan/s4882/reset.c b/src/mainboard/tyan/s4882/reset.c
new file mode 100644
index 0000000000..7f58d01410
--- /dev/null
+++ b/src/mainboard/tyan/s4882/reset.c
@@ -0,0 +1,6 @@
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+ amd8111_hard_reset(0, 1);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 12:53:04 +0000