diff options
Diffstat (limited to 'src/mainboard/tyan/s4882')
| -rw-r--r-- | src/mainboard/tyan/s4882/Config.lb | 8 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/Options.lb | 26 | ||||
| -rw-r--r-- | src/mainboard/tyan/s4882/cache_as_ram_auto.c | 352 |
3 files changed, 95 insertions, 291 deletions
diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 18fec090cf..1913120393 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -103,9 +103,13 @@ end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds + if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb index 2411f0f384..57e10153a1 100644 --- a/src/mainboard/tyan/s4882/Options.lb +++ b/src/mainboard/tyan/s4882/Options.lb @@ -52,13 +52,17 @@ uses OBJCOPY uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_E0_MEM_HOLE_SIZEK +uses K8_HW_MEM_HOLE_SIZEK uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + ### ### Build options ### @@ -71,7 +75,9 @@ default ROM_SIZE=524288 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 ## ## Build code for the fallback boot @@ -120,20 +126,24 @@ default CONFIG_LOGICAL_CPUS=1 default CONFIG_CHIP_NAME=1 #1G memory hole -default K8_E0_MEM_HOLE_SIZEK=0x100000 +default K8_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 +#default CONFIG_CONSOLE_VGA=1 +#default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=0 +default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=1 + +default ENABLE_APIC_EXT_ID=1 +default APIC_ID_OFFSET=0x10 +default LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC @@ -173,7 +183,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## ## LinuxBIOS C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default _RAMBASE=0x00002000 ## ## Load the payload from the ROM diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index 234e3a0a58..237d9c94f1 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -14,7 +14,6 @@ #include "ram/ramtest.c" #include "northbridge/amd/amdk8/cpu_rev.c" -#define K8_HT_FREQ_1G_SUPPORT 0 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -37,28 +36,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ -static unsigned node_link_to_bus(unsigned node, unsigned link) -{ - unsigned reg; - - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((((config_map >> 4) & 7) == node) && - (((config_map >> 8) & 3) == link)) - { - return (config_map >> 16) & 0xff; - } - } - return 0; -} - static void hard_reset(void) { device_t dev; @@ -117,6 +94,21 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } +#if 0 +static inline void change_i2c_mux(unsigned device) +{ +#define SMBUS_HUB 0x18 + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); +} +#endif static inline int spd_read_byte(unsigned device, unsigned address) { @@ -126,13 +118,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/raminit.c" -#if 0 - #define ENABLE_APIC_EXT_ID 1 - #define APIC_ID_OFFSET 0x10 - #define LIFT_BSP_APIC_ID 0 -#else - #define ENABLE_APIC_EXT_ID 0 -#endif #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" @@ -141,17 +126,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 -#include "cpu/amd/dualcore/dualcore.c" -#else -#include "cpu/amd/model_fxx/node_id.c" #endif -#define FIRST_CPU 1 -#define SECOND_CPU 1 - -#define THIRD_CPU 1 -#define FOURTH_CPU 1 - -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU) +#include "cpu/amd/dualcore/dualcore.c" #define RC0 ((1<<2)<<8) #define RC1 ((1<<1)<<8) @@ -165,43 +141,22 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + #if USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void real_main(unsigned long bist); - -void amd64_main(unsigned long bist) +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { -#if CONFIG_LOGICAL_CPUS==1 - struct node_core_id id; -#else - unsigned nodeid; -#endif - /* Make cerain my local apic is useable */ -// enable_lapic(); - -#if CONFIG_LOGICAL_CPUS==1 - id = get_node_core_id_x(); - /* Is this a cpu only reset? */ - if (cpu_init_detected(id.nodeid)) { -#else -// nodeid = lapicid(); - nodeid = get_node_id(); - /* Is this a cpu only reset? */ - if (cpu_init_detected(nodeid)) { -#endif - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } + unsigned last_boot_normal_x = last_boot_normal(); - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { goto normal_image; } else { goto fallback_image; @@ -213,11 +168,10 @@ void amd64_main(unsigned long bist) enumerate_ht_chain(); - /* Setup the ck804 */ amd8111_enable_rom(); /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { + if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } /* This is the primary cpu how should I boot? */ @@ -230,147 +184,55 @@ void amd64_main(unsigned long bist) normal_image: __asm__ volatile ("jmp __normal_image" : /* outputs */ - : "a" (bist) /* inputs */ + : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */ ); - cpu_reset: -#if 0 - //CPU reset will reset memtroller ??? - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - ); -#endif fallback_image: - real_main(bist); + ; } -void real_main(unsigned long bist) -#else -void amd64_main(unsigned long bist) #endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, - .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, - .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, - - }, + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); #endif + real_main(bist, cpu_init_detectedx); -#if THIRD_CPU - { - .node_id = 2, - .f0 = PCI_DEV(0, 0x1a, 0), - .f1 = PCI_DEV(0, 0x1a, 1), - .f2 = PCI_DEV(0, 0x1a, 2), - .f3 = PCI_DEV(0, 0x1a, 3), - .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, - .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, - - }, +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, #endif -#if FOURTH_CPU - { - .node_id = 3, - .f0 = PCI_DEV(0, 0x1b, 0), - .f1 = PCI_DEV(0, 0x1b, 1), - .f2 = PCI_DEV(0, 0x1b, 2), - .f3 = PCI_DEV(0, 0x1b, 3), - .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, - .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, - - }, +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + RC3|DIMM0, RC3|DIMM2, 0, 0, + RC3|DIMM1, RC3|DIMM3, 0, 0, #endif }; int needs_reset; unsigned cpu_reset = 0; + unsigned bsp_apicid = 0; - if (bist == 0) { -#if CONFIG_LOGICAL_CPUS==1 - struct node_core_id id; -#else - unsigned nodeid; -#endif - /* Skip this if there was a built in self test failure */ -// amd_early_mtrr_init(); # don't need, already done in cache_as_ram - -#if CONFIG_LOGICAL_CPUS==1 - set_apicid_cpuid_lo(); - id = get_node_core_id_x(); // that is initid - #if ENABLE_APIC_EXT_ID == 1 - if(id.coreid == 0) { - enable_apic_ext_id(id.nodeid); - } - #endif -#else - nodeid = get_node_id(); - #if ENABLE_APIC_EXT_ID == 1 - enable_apic_ext_id(nodeid); - #endif -#endif - - enable_lapic(); - init_timer(); + struct mem_controller ctrl[8]; + unsigned nodes; - -#if CONFIG_LOGICAL_CPUS==1 - #if ENABLE_APIC_EXT_ID == 1 - #if LIFT_BSP_APIC_ID == 0 - if( id.nodeid != 0 ) //all except cores in node0 - #endif - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); - #endif - if(id.coreid == 0) { - if (cpu_init_detected(id.nodeid)) { - cpu_reset = 1; - goto cpu_reset_x; - } - distinguish_cpu_resets(id.nodeid); - } -#else - #if ENABLE_APIC_EXT_ID == 1 - #if LIFT_BSP_APIC_ID == 0 - if(nodeid != 0) - #endif - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 - - #endif - if (cpu_init_detected(nodeid)) { - cpu_reset = 1; - goto cpu_reset_x; - } - distinguish_cpu_resets(nodeid); -#endif - - if (!boot_cpu() -#if CONFIG_LOGICAL_CPUS==1 - || (id.coreid != 0) -#endif - ) { - // We need stop the CACHE as RAM for this CPU too - #include "cpu/amd/car/cache_as_ram_post.c" - stop_this_cpu(); // it will stop all cores except core0 of cpu0 - } + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); } + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -379,13 +241,18 @@ void amd64_main(unsigned long bist) report_bist_failure(bist); setup_s4882_resource_map(); - + needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched + wait_all_core0_started(); start_other_cores(); #endif + + wait_all_aps_started(bsp_apicid); + + // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { @@ -393,94 +260,17 @@ void amd64_main(unsigned long bist) soft_reset(); } + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + enable_smbus(); memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - -#if 1 - { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n\t" - : "=a" (v_esp) - ); -#if CONFIG_USE_INIT - printk_debug("v_esp=%08x\r\n", v_esp); -#else - print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); -#endif - } -#endif - -#if 1 - - -cpu_reset_x: - -#if CONFIG_USE_INIT - printk_debug("cpu_reset = %08x\r\n",cpu_reset); -#else - print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); -#endif - - if(cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ( - "movl %0, %%ebx\n\t" - ::"a" (cpu_reset) - ); - - if(cpu_reset==0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/amd/car/cache_as_ram_post.c" - } - else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/amd/car/cache_as_ram_post.c" - } - - __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ( - "movl %%ebx, %0\n\t" - :"=a" (new_cpu_reset) - ); - - print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/ - if(new_cpu_reset==0) { - print_debug("done\r\n"); - } else - { - print_debug("\r\n"); - } - -#if CONFIG_USE_INIT - printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); -#endif - /*copy and execute linuxbios_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } -#endif - + sdram_initialize(nodes, ctrl); - print_debug("should not be here -\r\n"); + post_cache_as_ram(cpu_reset); } |