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-rw-r--r--src/mainboard/tyan/s1846/romstage.c4
-rw-r--r--src/mainboard/tyan/s2735/romstage.c7
-rw-r--r--src/mainboard/tyan/s2850/romstage.c3
-rw-r--r--src/mainboard/tyan/s2875/romstage.c3
-rw-r--r--src/mainboard/tyan/s2880/romstage.c4
-rw-r--r--src/mainboard/tyan/s2881/romstage.c6
-rw-r--r--src/mainboard/tyan/s2882/romstage.c3
-rw-r--r--src/mainboard/tyan/s2885/romstage.c5
-rw-r--r--src/mainboard/tyan/s2891/romstage.c4
-rw-r--r--src/mainboard/tyan/s2892/romstage.c4
-rw-r--r--src/mainboard/tyan/s2895/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912/romstage.c5
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c3
-rw-r--r--src/mainboard/tyan/s4880/romstage.c3
-rw-r--r--src/mainboard/tyan/s4882/romstage.c4
15 files changed, 13 insertions, 49 deletions
diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c
index af9e582639..6c1ba5891a 100644
--- a/src/mainboard/tyan/s1846/romstage.c
+++ b/src/mainboard/tyan/s1846/romstage.c
@@ -18,9 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-
-
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@@ -71,3 +68,4 @@ static void main(unsigned long bist)
sdram_enable();
/* ram_check(0, 640 * 1024); */
}
+
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index c339740bde..8ca9c5cba5 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -72,12 +70,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-
#include "northbridge/intel/e7501/raminit.c"
#include "northbridge/intel/e7501/reset_test.c"
#include "lib/generic_sdram.c"
-
#include "cpu/x86/car/copy_and_run.c"
void amd64_main(unsigned long bist)
@@ -135,7 +131,6 @@ void amd64_main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
-
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
@@ -222,7 +217,7 @@ cpu_reset_x:
}
#endif
-
print_debug("should not be here -\r\n");
}
+
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index cf0b71edcc..22eecc9ec9 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -157,3 +155,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 26c291cfd5..e57c3642b5 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -157,3 +155,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index b5565fb35a..2dbcdbebf1 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -15,7 +13,6 @@
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
@@ -159,3 +156,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index bbe6d68e0a..b47bf584e8 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
@@ -83,7 +80,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@@ -91,7 +87,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -186,3 +181,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 3d27fce4cf..d801abbdc9 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -163,3 +161,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index 3dd5fb7194..a6e4f8e2cc 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -91,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#endif
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -165,7 +162,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
soft_reset();
}
-
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
@@ -184,3 +180,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index bc0ccb9db7..838c71c316 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
//used by raminit
#define QRANK_DIMM_SUPPORT 1
@@ -203,3 +200,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 7ccffc076a..099c29aa36 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
@@ -172,3 +169,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 2d38b635d4..98ac94c3e1 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
#define K8_ALLOCATE_IO_RANGE 1
#define QRANK_DIMM_SUPPORT 1
@@ -217,3 +214,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 1e2f725198..0db72dff24 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-
-
#define RAMINIT_SYSINFO 1
#define K8_ALLOCATE_IO_RANGE 1
@@ -144,7 +141,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-
static void sio_setup(void)
{
@@ -208,7 +204,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-
#if CONFIG_USBDEBUG_DIRECT
mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init();
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index caf6c18dac..9081945511 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ASSEMBLY 1
-
-
#define RAMINIT_SYSINFO 1
#define FAM10_SCAN_PCI_BUS 0
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 49f7f16a19..804531b0cd 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -208,3 +206,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index a3ee6cd641..6dd2b042b0 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
#include <stdint.h>
#include <string.h>
@@ -33,7 +31,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
static void memreset_setup(void)
@@ -199,3 +196,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 07:46:47 +0000