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-rw-r--r--src/mainboard/tyan/s2912/romstage.c7
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c5
2 files changed, 2 insertions, 10 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 2f0ef20916..20b6baadbd 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -23,11 +23,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -205,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 61c253bf47..8439740ffb 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -27,9 +27,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -216,7 +213,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);