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Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2912/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c6
2 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index f6116f978b..eae4428c49 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -136,10 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
- early_usbdebug_init();
-#endif
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index ed3ee8b4b4..3699d09777 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
- printk(BIOS_DEBUG, "\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
- early_usbdebug_init();
-#endif
-
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);